4c95d46303
For 1000Mb mode to work reliably TX/RX delays need to be configured between the TX/RX clock and the respective signals on the PHY to compensate for differing trace lengths on the PCB. Reviewed by: manu MFC after: 1 week
196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/dwc/if_dwc.h>
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#include <dev/dwc/if_dwcvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/syscon/syscon.h>
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#include "syscon_if.h"
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#include "if_dwc_if.h"
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#define RK3328_GRF_MAC_CON0 0x0900
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#define RK3328_GRF_MAC_CON0_TX_MASK 0x7F
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#define RK3328_GRF_MAC_CON0_TX_SHIFT 0
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#define RK3328_GRF_MAC_CON0_RX_MASK 0x7F
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#define RK3328_GRF_MAC_CON0_RX_SHIFT 7
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#define RK3328_GRF_MAC_CON1 0x0904
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#define RK3328_GRF_MAC_CON1_RX_ENA (1 << 1)
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#define RK3328_GRF_MAC_CON1_TX_ENA (1 << 0)
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#define RK3328_GRF_MAC_CON2 0x0908
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#define RK3328_GRF_MACPHY_CON0 0x0B00
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#define RK3328_GRF_MACPHY_CON1 0x0B04
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#define RK3328_GRF_MACPHY_CON2 0x0B08
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#define RK3328_GRF_MACPHY_CON3 0x0B0C
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#define RK3328_GRF_MACPHY_STATUS 0x0B10
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,rk3288-gmac", 1},
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{"rockchip,rk3328-gmac", 1},
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{"rockchip,rk3399-gmac", 1},
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{NULL, 0}
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};
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static void
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rk3328_set_delays(struct syscon *grf, phandle_t node)
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{
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uint32_t tx, rx;
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if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0)
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tx = 0x30;
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if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0)
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rx = 0x10;
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if (bootverbose)
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printf("setting RK3328 RX/TX delays: %d/%d\n", rx, tx);
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tx = ((tx & RK3328_GRF_MAC_CON0_TX_MASK) <<
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RK3328_GRF_MAC_CON0_TX_SHIFT);
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rx = ((rx & RK3328_GRF_MAC_CON0_TX_MASK) <<
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RK3328_GRF_MAC_CON0_RX_SHIFT);
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SYSCON_WRITE_4(grf, RK3328_GRF_MAC_CON0, tx | rx | 0xFFFF0000);
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SYSCON_WRITE_4(grf, RK3328_GRF_MAC_CON1, RK3328_GRF_MAC_CON1_TX_ENA | RK3328_GRF_MAC_CON1_RX_ENA |
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((RK3328_GRF_MAC_CON1_TX_ENA | RK3328_GRF_MAC_CON1_RX_ENA) << 16));
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}
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#define RK3399_GRF_SOC_CON6 0xc218
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#define RK3399_GRF_SOC_CON6_TX_ENA (1 << 7)
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#define RK3399_GRF_SOC_CON6_TX_MASK 0x7F
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#define RK3399_GRF_SOC_CON6_TX_SHIFT 0
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#define RK3399_GRF_SOC_CON6_RX_MASK 0x7F
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#define RK3399_GRF_SOC_CON6_RX_ENA (1 << 15)
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#define RK3399_GRF_SOC_CON6_RX_SHIFT 8
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static void
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rk3399_set_delays(struct syscon *grf, phandle_t node)
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{
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uint32_t tx, rx;
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if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0)
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tx = 0x30;
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if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0)
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rx = 0x10;
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if (bootverbose)
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printf("setting RK3399 RX/TX delays: %d/%d\n", rx, tx);
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tx = ((tx & RK3399_GRF_SOC_CON6_TX_MASK) <<
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RK3399_GRF_SOC_CON6_TX_SHIFT) | RK3399_GRF_SOC_CON6_TX_ENA;
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rx = ((rx & RK3399_GRF_SOC_CON6_TX_MASK) <<
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RK3399_GRF_SOC_CON6_RX_SHIFT) | RK3399_GRF_SOC_CON6_RX_ENA;
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SYSCON_WRITE_4(grf, RK3399_GRF_SOC_CON6, tx | rx | 0xFFFF0000);
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}
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static int
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if_dwc_rk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Rockchip Gigabit Ethernet Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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if_dwc_rk_init(device_t dev)
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{
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phandle_t node;
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struct syscon *grf = NULL;
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node = ofw_bus_get_node(dev);
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if (OF_hasprop(node, "rockchip,grf") &&
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syscon_get_by_ofw_property(dev, node,
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"rockchip,grf", &grf) != 0) {
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device_printf(dev, "cannot get grf driver handle\n");
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return (ENXIO);
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}
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if (ofw_bus_is_compatible(dev, "rockchip,rk3399-gmac"))
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rk3399_set_delays(grf, node);
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else if (ofw_bus_is_compatible(dev, "rockchip,rk3328-gmac"))
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rk3328_set_delays(grf, node);
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/* Mode should be set according to dtb property */
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return (0);
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}
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static int
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if_dwc_rk_mac_type(device_t dev)
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{
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return (DWC_GMAC_NORMAL_DESC);
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}
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static int
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if_dwc_rk_mii_clk(device_t dev)
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{
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/* Should be calculated from the clock */
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return (GMAC_MII_CLK_150_250M_DIV102);
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}
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static device_method_t if_dwc_rk_methods[] = {
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DEVMETHOD(device_probe, if_dwc_rk_probe),
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DEVMETHOD(if_dwc_init, if_dwc_rk_init),
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DEVMETHOD(if_dwc_mac_type, if_dwc_rk_mac_type),
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DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk),
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DEVMETHOD_END
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};
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static devclass_t dwc_rk_devclass;
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extern driver_t dwc_driver;
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DEFINE_CLASS_1(dwc, dwc_rk_driver, if_dwc_rk_methods,
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sizeof(struct dwc_softc), dwc_driver);
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DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, dwc_rk_devclass, 0, 0);
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MODULE_DEPEND(dwc_rk, dwc, 1, 1, 1);
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