94bc2117b4
- Add CCM driver and clocks implementations for i.MX 8M - Add GPC driver for iMX8 - Add clock tree for i.MX 8M Quad - Add clocks support and new compat strings (where required) for existing i.MX 6 UART, I2C, and GPIO drivers - Enable aarch64-compatible drivers form i.MX 6 in arm64 GENERIC kernel config - Add dtb/imx8 kernel module with DTBs for Nitrogen8M and iMX8MQ EVK With this patch both Nitrogen8M and iMX8MQ EVK boot with NFS root up to multiuser login prompt Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25274
174 lines
5.4 KiB
C
174 lines
5.4 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __IMX8MQ_CCM_H__
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#define __IMX8MQ_CCM_H__
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#define IMX8MQ_CLK_DUMMY 0
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#define IMX8MQ_CLK_32K 1
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#define IMX8MQ_CLK_25M 2
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#define IMX8MQ_CLK_27M 3
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#define IMX8MQ_CLK_EXT1 4
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#define IMX8MQ_CLK_EXT2 5
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#define IMX8MQ_CLK_EXT3 6
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#define IMX8MQ_CLK_EXT4 7
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#define IMX8MQ_ARM_PLL_REF_SEL 8
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#define IMX8MQ_ARM_PLL_REF_DIV 9
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#define IMX8MQ_ARM_PLL 10
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#define IMX8MQ_ARM_PLL_BYPASS 11
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#define IMX8MQ_ARM_PLL_OUT 12
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#define IMX8MQ_GPU_PLL_REF_SEL 13
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#define IMX8MQ_GPU_PLL_REF_DIV 14
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#define IMX8MQ_GPU_PLL 15
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#define IMX8MQ_GPU_PLL_BYPASS 16
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#define IMX8MQ_GPU_PLL_OUT 17
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#define IMX8MQ_VPU_PLL_REF_SEL 18
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#define IMX8MQ_VPU_PLL_REF_DIV 19
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#define IMX8MQ_VPU_PLL 20
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#define IMX8MQ_VPU_PLL_BYPASS 21
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#define IMX8MQ_VPU_PLL_OUT 22
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#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
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#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
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#define IMX8MQ_AUDIO_PLL1 25
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#define IMX8MQ_AUDIO_PLL1_BYPASS 26
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#define IMX8MQ_AUDIO_PLL1_OUT 27
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#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
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#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
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#define IMX8MQ_AUDIO_PLL2 30
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#define IMX8MQ_AUDIO_PLL2_BYPASS 31
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#define IMX8MQ_AUDIO_PLL2_OUT 32
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#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
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#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
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#define IMX8MQ_VIDEO_PLL1 35
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#define IMX8MQ_VIDEO_PLL1_BYPASS 36
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#define IMX8MQ_VIDEO_PLL1_OUT 37
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#define IMX8MQ_SYS3_PLL1_REF_SEL 54
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#define IMX8MQ_SYS3_PLL1 56
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#define IMX8MQ_DRAM_PLL1_REF_SEL 62
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#define IMX8MQ_SYS1_PLL_40M 70
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#define IMX8MQ_SYS1_PLL_80M 71
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#define IMX8MQ_SYS1_PLL_100M 72
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#define IMX8MQ_SYS1_PLL_133M 73
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#define IMX8MQ_SYS1_PLL_160M 74
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#define IMX8MQ_SYS1_PLL_200M 75
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#define IMX8MQ_SYS1_PLL_266M 76
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#define IMX8MQ_SYS1_PLL_400M 77
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#define IMX8MQ_SYS1_PLL_800M 78
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#define IMX8MQ_SYS2_PLL_50M 79
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#define IMX8MQ_SYS2_PLL_100M 80
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#define IMX8MQ_SYS2_PLL_125M 81
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#define IMX8MQ_SYS2_PLL_166M 82
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#define IMX8MQ_SYS2_PLL_200M 83
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#define IMX8MQ_SYS2_PLL_250M 84
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#define IMX8MQ_SYS2_PLL_333M 85
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#define IMX8MQ_SYS2_PLL_500M 86
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#define IMX8MQ_SYS2_PLL_1000M 87
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#define IMX8MQ_CLK_ENET_AXI 104
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#define IMX8MQ_CLK_USB_BUS 110
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#define IMX8MQ_CLK_AHB 116
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#define IMX8MQ_CLK_ENET_REF 137
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#define IMX8MQ_CLK_ENET_TIMER 138
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#define IMX8MQ_CLK_ENET_PHY_REF 139
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#define IMX8MQ_CLK_USDHC1 142
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#define IMX8MQ_CLK_USDHC2 143
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#define IMX8MQ_CLK_I2C1 144
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#define IMX8MQ_CLK_I2C2 145
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#define IMX8MQ_CLK_I2C3 146
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#define IMX8MQ_CLK_I2C4 147
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#define IMX8MQ_CLK_UART1 148
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#define IMX8MQ_CLK_UART2 149
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#define IMX8MQ_CLK_UART3 150
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#define IMX8MQ_CLK_UART4 151
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#define IMX8MQ_CLK_USB_CORE_REF 152
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#define IMX8MQ_CLK_USB_PHY_REF 153
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#define IMX8MQ_CLK_ENET1_ROOT 182
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#define IMX8MQ_CLK_I2C1_ROOT 184
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#define IMX8MQ_CLK_I2C2_ROOT 185
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#define IMX8MQ_CLK_I2C3_ROOT 186
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#define IMX8MQ_CLK_I2C4_ROOT 187
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#define IMX8MQ_CLK_UART1_ROOT 202
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#define IMX8MQ_CLK_UART2_ROOT 203
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#define IMX8MQ_CLK_UART3_ROOT 204
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#define IMX8MQ_CLK_UART4_ROOT 205
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#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
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#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
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#define IMX8MQ_CLK_USB1_PHY_ROOT 208
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#define IMX8MQ_CLK_USB2_PHY_ROOT 209
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#define IMX8MQ_CLK_USDHC1_ROOT 210
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#define IMX8MQ_CLK_USDHC2_ROOT 211
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#define IMX8MQ_SYS1_PLL_OUT 231
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#define IMX8MQ_SYS2_PLL_OUT 232
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#define IMX8MQ_SYS3_PLL_OUT 233
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#define IMX8MQ_CLK_IPG_ROOT 236
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#define IMX8MQ_CLK_GPIO1_ROOT 259
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#define IMX8MQ_CLK_GPIO2_ROOT 260
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#define IMX8MQ_CLK_GPIO3_ROOT 261
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#define IMX8MQ_CLK_GPIO4_ROOT 262
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#define IMX8MQ_CLK_GPIO5_ROOT 263
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#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
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#define IMX8MQ_SYS1_PLL_40M_CG 267
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#define IMX8MQ_SYS1_PLL_80M_CG 268
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#define IMX8MQ_SYS1_PLL_100M_CG 269
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#define IMX8MQ_SYS1_PLL_133M_CG 270
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#define IMX8MQ_SYS1_PLL_160M_CG 271
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#define IMX8MQ_SYS1_PLL_200M_CG 272
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#define IMX8MQ_SYS1_PLL_266M_CG 273
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#define IMX8MQ_SYS1_PLL_400M_CG 274
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#define IMX8MQ_SYS1_PLL_800M_CG 275
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#define IMX8MQ_SYS2_PLL_50M_CG 276
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#define IMX8MQ_SYS2_PLL_100M_CG 277
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#define IMX8MQ_SYS2_PLL_125M_CG 278
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#define IMX8MQ_SYS2_PLL_166M_CG 279
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#define IMX8MQ_SYS2_PLL_200M_CG 280
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#define IMX8MQ_SYS2_PLL_250M_CG 281
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#define IMX8MQ_SYS2_PLL_333M_CG 282
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#define IMX8MQ_SYS2_PLL_500M_CG 283
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#define IMX8MQ_SYS2_PLL_1000M_CG 284
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#endif
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