33368e9fe8
sun4v nexus(4) in turn is based on):
o Change nexus(4) to manage the resources of its children so the
respective device drivers don't need to figure them out of OFW
themselves.
o Change nexus(4) to provide the ofw_bus KOBJ interface instead of
using IVARs for supplying the OFW node and the subset of standard
properties of its children. Together with the previous change this
also allows to fully take advantage of newbus in that drivers like
fhc(4), which attach on multiple parent busses, no longer require
different bus front-ends as obtaining the OFW node and properties
as well as resource allocation works the same for all supported
busses. As such this change also is part 4/4 of allowing creator(4)
to work in USIII-based machines as it allows this driver to attach
on both nexus(4) and upa(4). On the other hand removing these IVARs
breaks API compatibility with the powerpc nexus(4) but which isn't
that bad as a) sparc64 currently doesn't share any device driver
hanging off of nexus(4) with powerpc and b) they were no longer
compatible regarding OFW-related extensions at the pci(4) level
since quite some time.
o Provide bus_get_dma_tag methods in nexus(4) and its children in
order to handle DMA tags in a hierarchical way and get rid of the
sparc64_root_dma_tag kludge. Together with the previous two items
this changes also allows to completely get rid of the nexus(4)
IVAR interface. It also includes:
- pushing the constraints previously specified by the nexus_dmatag
down into the DMA tags of psycho(4) and sbus(4) as it's their
IOMMUs which induce these restrictions (and nothing at the
nexus(4) or anything that would warrant specifying them there),
- fixing some obviously wrong constraints of the psycho(4) and
sbus(4) DMA tags, which happened to not actually be used with
the sparc64_root_dma_tag kludge in place and therefore didn't
cause problems so far,
- replacing magic constants for constraints with macros as far
as it is obvious as to where they come from.
This doesn't include taking advantage of the newbus way to get
the parent DMA tags implemented by this change in order to divorce
the IOTSBs of the PCI and SBus IOMMUs or for implementing the
workaround for the DMA sync bug in Sabre (and Tomatillo) bridges,
yet, though.
o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus
by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied
from ofw_upa.h) and renaming its content, which actually applies to
all of Fireplane/Safari, JBus and UPA (in the host bus case), as
appropriate.
o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for
allocating the device info for the children of nexus(4). This is
done in order to not need to export M_NEXUS when deriving drivers
for subordinate busses from the nexus(4) class.
o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so
we can derive subclasses from it.
o Const'ify the nexus_excl_name and nexus_excl_type arrays as well
as add 'associations' and 'rsc', which are pseudo-devices without
resources and therefore of no real interest for nexus(4), to the
former.
o Let the nexus(4) device memory rman manage the entire 64-bit address
space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as
Fireplane/Safari- and JBus-based machines use multiple ranges,
which can't be as easily divided as in the case of UPA (limiting
the address space only served for sanity checking anyway).
o Use M_WAITOK instead of M_NOWAIT when allocating the device info
for children of nexus(4) in order to give one less opportunity
for adding devices to nexus(4) to fail.
o While adapting the drivers affected by the above nexus(4) changes,
change them to take advantage of rman_get_rid() instead of caching
the RIDs assigned to allocated resources, now that the RIDs of
resources are correctly set.
o In iommu(4) and nexus(4) replace hard-coded functions names, which
actually became outdated in several places, in panic strings and
status massages with __func__. [1]
o Use driver_filter_t in prototypes where appropriate.
o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and
sbus(4) as I changed considerable amounts of these drivers as well
as added a bunch of new features, workarounds for silicon bugs etc.
o Fix some white space nits.
Due to lack of access to Exx00 hardware, these changes, i.e. central(4)
and fhc(4), couldn't be runtime tested on such a machine. Exx00 are
currently reported to panic before trying to attach nexus(4) anyway
though.
PR: 76052 [1]
Approved by: re (kensmith)
181 lines
6.3 KiB
C
181 lines
6.3 KiB
C
/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IOMMUREG_H_
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#define _MACHINE_IOMMUREG_H_
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/*
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* UltraSPARC IOMMU registers, common to both the PCI and SBus
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* controllers.
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*/
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/* iommmu registers */
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#define IMR_CTL 0x0000 /* IOMMU control register */
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#define IMR_TSB 0x0008 /* IOMMU TSB base register */
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#define IMR_FLUSH 0x0010 /* IOMMU flush register */
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/* streaming buffer registers */
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#define ISR_CTL 0x0000 /* streaming buffer control reg */
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#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
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#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
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/* streaming buffer diagnostics registers. */
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#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
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#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
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#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
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#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
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/* streaming buffer control register */
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#define STRBUF_EN 0x0000000000000001UL
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#define STRBUF_D 0x0000000000000002UL
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#define IOMMU_BITS 34
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#define IOMMU_MAXADDR ((1UL << IOMMU_BITS) - 1)
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/*
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* control register bits
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*/
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/* Nummber of entries in IOTSB */
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#define IOMMUCR_TSBSZ_SHIFT 16
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#define IOMMUCR_TSB1K 0x0000000000000000UL
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#define IOMMUCR_TSB2K 0x0000000000010000UL
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#define IOMMUCR_TSB4K 0x0000000000020000UL
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#define IOMMUCR_TSB8K 0x0000000000030000UL
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#define IOMMUCR_TSB16K 0x0000000000040000UL
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#define IOMMUCR_TSB32K 0x0000000000050000UL
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#define IOMMUCR_TSB64K 0x0000000000060000UL
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#define IOMMUCR_TSB128K 0x0000000000070000UL
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/* Mask for above */
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#define IOMMUCR_TSBMASK 0xfffffffffff8ffffUL
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/* 8K iommu page size */
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#define IOMMUCR_8KPG 0x0000000000000000UL
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/* 64K iommu page size */
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#define IOMMUCR_64KPG 0x0000000000000004UL
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/* Diag enable */
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#define IOMMUCR_DE 0x0000000000000002UL
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/* Enable IOMMU */
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#define IOMMUCR_EN 0x0000000000000001UL
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/*
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* Diagnostic register definitions.
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*/
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#define IOMMU_DTAG_VPNBITS 19
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#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
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#define IOMMU_DTAG_VPNSHIFT 13
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#define IOMMU_DTAG_ERRBITS 3
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#define IOMMU_DTAG_ERRSHIFT 22
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#define IOMMU_DTAG_ERRMASK \
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(((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
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#define IOMMU_DDATA_PGBITS 21
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#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
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#define IOMMU_DDATA_PGSHIFT 13
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#define IOMMU_DDATA_C (1 << 28)
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#define IOMMU_DDATA_V (1 << 30)
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/*
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* IOMMU stuff
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*/
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/* Entry valid */
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#define IOTTE_V 0x8000000000000000UL
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/* 8K or 64K page? */
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#define IOTTE_64K 0x2000000000000000UL
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#define IOTTE_8K 0x0000000000000000UL
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/* Is page streamable? */
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#define IOTTE_STREAM 0x1000000000000000UL
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/* Accesses to same bus segment? */
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#define IOTTE_LOCAL 0x0800000000000000UL
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/* Let's assume this is correct */
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#define IOTTE_PAMASK 0x000001ffffffe000UL
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/* Accesses to cacheable space */
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#define IOTTE_C 0x0000000000000010UL
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/* Writeable */
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#define IOTTE_W 0x0000000000000002UL
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/* log2 of the IOMMU TTE size. */
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#define IOTTE_SHIFT 3
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/* Streaming buffer line size. */
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#define STRBUF_LINESZ 64
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/*
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* Number of bytes written by a stream buffer flushsync operation to indicate
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* completion.
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*/
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#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
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/*
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* On sun4u each bus controller has a separate IOMMU. The IOMMU has
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* a TSB which must be page aligned and physically contiguous. Mappings
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* can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
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* with the CPU's MMU.
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*
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* On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
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* following size segments:
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*
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* VA size VA base TSB size tsbsize
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* -------- -------- --------- -------
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* 8MB ff800000 8K 0
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* 16MB ff000000 16K 1
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* 32MB fe000000 32K 2
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* 64MB fc000000 64K 3
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* 128MB f8000000 128K 4
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* 256MB f0000000 256K 5
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* 512MB e0000000 512K 6
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* 1GB c0000000 1MB 7
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*
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* Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
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* this scheme to determine the IOVA base address. Instead, bits 31-29 are
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* used to check against the Target Address Space register in the IIi and
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* the the IOMMU is used if they hit. God knows what goes on in the IIe.
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*
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*/
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#define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
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#define IOTSB_VEND (~IO_PAGE_MASK)
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#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
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#define MAKEIOTTE(pa,w,c,s) \
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(((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
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((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
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(IOTTE_V | IOTTE_8K))
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#define IOTSBSLOT(va) \
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((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
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#endif /* !_MACHINE_IOMMUREG_H_ */
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