7af87ea720
SPI drivers for the various Ralink/Mediatek SoCs. There are 2 versions of the SPI controller (so far) present in the supported SoCs, hence v1 and v2 drivers. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5842
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* Copyright (c) 2011, Aleksandr Rybalko <ray@FreeBSD.org>
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* Copyright (c) 2013, Alexander A. Mityaev <sansan@adm.ua>
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* Copyright (c) 2016, Stanislav Galabov <sgalabov@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MTK_SPIVAR_H_
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#define _MTK_SPIVAR_H_
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/* SPI controller interface */
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#define MTK_SPISTAT 0x00
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/* SPIBUSY is alias for SPIBUSY, because SPISTAT have only BUSY bit*/
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#define MTK_SPIBUSY MTK_SPISTAT
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#define MTK_SPICFG 0x10
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#define MSBFIRST (1<<8)
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#define SPICLKPOL (1<<6)
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#define CAPT_ON_CLK_FALL (1<<5)
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#define TX_ON_CLK_FALL (1<<4)
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#define HIZSPI (1<<3) /* Set SPI pins to Tri-state */
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#define SPI_CLK_SHIFT 0 /* SPI clock divide control */
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#define SPI_CLK_MASK 0x00000007
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#define SPI_CLK_DIV2 0
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#define SPI_CLK_DIV4 1
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#define SPI_CLK_DIV8 2
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#define SPI_CLK_DIV16 3
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#define SPI_CLK_DIV32 4
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#define SPI_CLK_DIV64 5
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#define SPI_CLK_DIV128 6
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#define SPI_CLK_DISABLED 7
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#define MTK_SPICTL 0x14
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#define HIZSMOSI (1<<3)
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#define START_WRITE (1<<2)
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#define START_READ (1<<1)
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#define CS_HIGH (1<<0)
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#define MTK_SPIDATA 0x20
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#define SPIDATA_MASK 0x000000ff
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#define MTK_SPI_WRITE 1
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#define MTK_SPI_READ 0
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#endif /* _MTK_SPIVAR_H_ */
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