34255ec554
boot all the way yet, but it's darn close (blows up somewhere probing the PS/2 mouse on the EISA bus).
782 lines
19 KiB
C
782 lines
19 KiB
C
/* $FreeBSD$ */
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/*
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* Copyright (c) 2000 Matthew Jacob
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/swiz.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/resource.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <alpha/mcbus/mcbusreg.h>
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#include <alpha/mcbus/mcbusvar.h>
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#include <alpha/mcbus/mcpciareg.h>
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#include <alpha/mcbus/mcpciavar.h>
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#include <alpha/pci/pcibus.h>
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#include <pci/pcivar.h>
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static devclass_t mcpcia_devclass;
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/* We're only allowing for one MCBUS right now */
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static device_t mcpcias[MCPCIA_PER_MCBUS];
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#define KV(pa) ((void *)ALPHA_PHYS_TO_K0SEG(pa))
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struct mcpcia_softc {
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struct mcpcia_softc *next;
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device_t dev; /* backpointer */
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u_int64_t sysbase; /* shorthand */
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* sparse i/o */
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int mcpcia_inst; /* our mcpcia instance # */
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};
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static struct mcpcia_softc *mcpcia_eisa = NULL;
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static int mcpcia_probe(device_t dev);
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static int mcpcia_attach(device_t dev);
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static int mcpcia_setup_intr(device_t, device_t, struct resource *, int,
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driver_intr_t *, void *, void **);
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static int
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mcpcia_teardown_intr(device_t, device_t, struct resource *, void *);
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static driver_intr_t mcpcia_intr;
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static device_method_t mcpcia_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mcpcia_probe),
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DEVMETHOD(device_attach, mcpcia_attach),
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/* Bus interface */
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DEVMETHOD(bus_setup_intr, mcpcia_setup_intr),
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DEVMETHOD(bus_teardown_intr, mcpcia_teardown_intr),
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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{ 0, 0 }
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};
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static driver_t mcpcia_driver = {
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"mcpcia", mcpcia_methods, sizeof (struct mcpcia_softc)
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};
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/*
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* SGMAP window for ISA: 8M at 8M
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*/
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#define MCPCIA_ISA_SG_MAPPED_BASE (8*1024*1024)
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#define MCPCIA_ISA_SG_MAPPED_SIZE (8*1024*1024)
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/*
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* Direct-mapped window: 2G at 2G
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*/
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#define MCPCIA_DIRECT_MAPPED_BASE (2UL*1024UL*1024UL*1024UL)
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#define MCPCIA_DIRECT_MAPPED_SIZE (2UL*1024UL*1024UL*1024UL)
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/*
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* SGMAP window for PCI: 1G at 1G
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*/
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#define MCPCIA_PCI_SG_MAPPED_BASE (1UL*1024UL*1024UL*1024UL)
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#define MCPCIA_PCI_SG_MAPPED_SIZE (1UL*1024UL*1024UL*1024UL)
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#define MCPCIA_SGTLB_INVALIDATE(sc) \
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do { \
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alpha_mb(); \
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REGVAL(MCPCIA_SG_TBIA(sc)) = 0xdeadbeef; \
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alpha_mb(); \
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} while (0)
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static void mcpcia_dma_init(struct mcpcia_softc *);
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static void mcpcia_sgmap_map(void *, vm_offset_t, vm_offset_t);
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#define MCPCIA_SOFTC(dev) (struct mcpcia_softc *) device_get_softc(dev)
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static struct mcpcia_softc *mcpcia_root;
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static alpha_chipset_inb_t mcpcia_inb;
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static alpha_chipset_inw_t mcpcia_inw;
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static alpha_chipset_inl_t mcpcia_inl;
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static alpha_chipset_outb_t mcpcia_outb;
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static alpha_chipset_outw_t mcpcia_outw;
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static alpha_chipset_outl_t mcpcia_outl;
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static alpha_chipset_readb_t mcpcia_readb;
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static alpha_chipset_readw_t mcpcia_readw;
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static alpha_chipset_readl_t mcpcia_readl;
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static alpha_chipset_writeb_t mcpcia_writeb;
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static alpha_chipset_writew_t mcpcia_writew;
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static alpha_chipset_writel_t mcpcia_writel;
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static alpha_chipset_maxdevs_t mcpcia_maxdevs;
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static alpha_chipset_cfgreadb_t mcpcia_cfgreadb;
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static alpha_chipset_cfgreadw_t mcpcia_cfgreadw;
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static alpha_chipset_cfgreadl_t mcpcia_cfgreadl;
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static alpha_chipset_cfgwriteb_t mcpcia_cfgwriteb;
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static alpha_chipset_cfgwritew_t mcpcia_cfgwritew;
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static alpha_chipset_cfgwritel_t mcpcia_cfgwritel;
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static alpha_chipset_t mcpcia_chipset = {
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mcpcia_inb,
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mcpcia_inw,
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mcpcia_inl,
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mcpcia_outb,
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mcpcia_outw,
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mcpcia_outl,
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mcpcia_readb,
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mcpcia_readw,
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mcpcia_readl,
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mcpcia_writeb,
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mcpcia_writew,
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mcpcia_writel,
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mcpcia_maxdevs,
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mcpcia_cfgreadb,
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mcpcia_cfgreadw,
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mcpcia_cfgreadl,
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mcpcia_cfgwriteb,
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mcpcia_cfgwritew,
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mcpcia_cfgwritel,
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};
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#define MCPCIA_NMBR(port) ((port >> 30) & 0x3)
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#define MCPCIA_INST(port) mcpcias[MCPCIA_NMBR(port)]
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#define MCPCIA_ADDR(port) (port & 0x3fffffff)
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static u_int8_t
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mcpcia_inb(u_int32_t port)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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if (port < (1 << 16)) {
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if (mcpcia_eisa == NULL) {
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return (0xff);
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}
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return SPARSE_READ_BYTE(mcpcia_eisa->io_base, port);
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}
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return SPARSE_READ_BYTE(sc->io_base, MCPCIA_ADDR(port));
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}
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static u_int16_t
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mcpcia_inw(u_int32_t port)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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if (port < (1 << 16)) {
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if (mcpcia_eisa == NULL) {
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return (0xffff);
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}
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return SPARSE_READ_WORD(mcpcia_eisa->io_base, port);
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}
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return SPARSE_READ_WORD(sc->io_base, MCPCIA_ADDR(port));
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}
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static u_int32_t
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mcpcia_inl(u_int32_t port)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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return SPARSE_READ_LONG(sc->io_base, MCPCIA_ADDR(port));
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}
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static void
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mcpcia_outb(u_int32_t port, u_int8_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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if (port < (1 << 16)) {
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if (mcpcia_eisa)
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SPARSE_WRITE_BYTE(mcpcia_eisa->io_base, port, data);
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} else {
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SPARSE_WRITE_BYTE(sc->io_base, MCPCIA_ADDR(port), data);
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}
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alpha_mb();
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}
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static void
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mcpcia_outw(u_int32_t port, u_int16_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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if (port < (1 << 16)) {
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if (mcpcia_eisa)
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SPARSE_WRITE_WORD(mcpcia_eisa->io_base, port, data);
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} else {
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SPARSE_WRITE_WORD(sc->io_base, MCPCIA_ADDR(port), data);
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}
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alpha_mb();
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}
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static void
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mcpcia_outl(u_int32_t port, u_int32_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(port));
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SPARSE_WRITE_LONG(sc->io_base, MCPCIA_ADDR(port), data);
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alpha_mb();
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}
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static u_int8_t
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mcpcia_readb(u_int32_t pa)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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return SPARSE_READ_BYTE(sc->smem_base, MCPCIA_ADDR(pa));
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}
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static u_int16_t
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mcpcia_readw(u_int32_t pa)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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return SPARSE_READ_WORD(sc->smem_base, MCPCIA_ADDR(pa));
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}
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static u_int32_t
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mcpcia_readl(u_int32_t pa)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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return SPARSE_READ_LONG(sc->smem_base, MCPCIA_ADDR(pa));
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}
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static void
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mcpcia_writeb(u_int32_t pa, u_int8_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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SPARSE_WRITE_BYTE(sc->smem_base, MCPCIA_ADDR(pa), data);
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alpha_mb();
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}
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static void
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mcpcia_writew(u_int32_t pa, u_int16_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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SPARSE_WRITE_WORD(sc->smem_base, MCPCIA_ADDR(pa), data);
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alpha_mb();
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}
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static void
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mcpcia_writel(u_int32_t pa, u_int32_t data)
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{
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struct mcpcia_softc *sc = MCPCIA_SOFTC(MCPCIA_INST(pa));
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SPARSE_WRITE_LONG(sc->smem_base, MCPCIA_ADDR(pa), data);
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alpha_mb();
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}
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static int
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mcpcia_maxdevs(u_int b)
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{
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return (MCPCIA_MAXDEV);
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}
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static u_int32_t mcpcia_cfgread(u_int, u_int, u_int, u_int, u_int, int);
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static void mcpcia_cfgwrite(u_int, u_int, u_int, u_int, u_int, int, u_int32_t);
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static u_int32_t
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mcpcia_cfgread(u_int bh, u_int bus, u_int slot, u_int func, u_int off, int sz)
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{
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device_t dev;
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struct mcpcia_softc *sc;
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u_int32_t *dp, data, rvp;
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u_int64_t paddr;
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int secondary = 0;
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rvp = data = ~0;
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if (bh > 3)
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return (data);
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dev = mcpcias[bh];
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if (dev == (device_t) 0) {
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return (data);
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}
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sc = MCPCIA_SOFTC(dev);
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/*
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* There's nothing in slot 0 on a primary bus.
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*
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* XXX: How do we generate knowledge of secondary bus accesses?
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*/
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if (secondary == 0 && (slot < 1 || slot >= MCPCIA_MAXDEV))
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return (data);
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paddr = secondary << 21;
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paddr |= slot << 16;
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paddr |= func << 13;
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paddr |= ((sz - 1) << 3);
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paddr |= ((unsigned long) ((off >> 2) << 7));
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paddr |= MCPCIA_PCI_CONF;
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paddr |= sc->sysbase;
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dp = (u_int32_t *)KV(paddr);
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#if 0
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printf("CFGREAD MID %d %d.%d.%d sz %d off %d -> paddr 0x%x",
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mcbus_get_mid(dev), secondary, slot, func, sz, off, paddr);
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#endif
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if (badaddr(dp, sizeof (*dp)) == 0) {
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data = *dp;
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}
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if (secondary) {
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}
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if (data != ~0) {
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if (sz == 1) {
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rvp = SPARSE_BYTE_EXTRACT(off, data);
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} else if (sz == 2) {
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rvp = SPARSE_WORD_EXTRACT(off, data);
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} else {
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rvp = data;
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}
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} else {
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rvp = data;
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}
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#if 0
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printf(" data 0x%x -> 0x%x\n", data, rvp);
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#endif
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return (rvp);
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}
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static void
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mcpcia_cfgwrite(u_int bh, u_int bus, u_int slot, u_int func, u_int off,
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int sz, u_int32_t data)
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{
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device_t dev;
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struct mcpcia_softc *sc;
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u_int32_t *dp;
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u_int64_t paddr;
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int secondary = 0;
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if (bh > 3)
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return;
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dev = mcpcias[bh];
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if (dev == (device_t) 0) {
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return;
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}
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sc = MCPCIA_SOFTC(dev);
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/*
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* There's nothing in slot 0 on a primary bus.
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*
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* XXX: How do we generate knowledge of secondary bus accesses?
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*/
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if (secondary == 0 && (slot < 1 || slot >= MCPCIA_MAXDEV))
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return;
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paddr = secondary << 21;
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paddr |= slot << 16;
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paddr |= func << 13;
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paddr |= ((sz - 1) << 3);
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paddr |= ((unsigned long) ((off >> 2) << 7));
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paddr |= MCPCIA_PCI_CONF;
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paddr |= sc->sysbase;
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dp = (u_int32_t *)KV(paddr);
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if (badaddr(dp, sizeof (*dp)) == 0) {
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u_int32_t new_data;
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if (sz == 1) {
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new_data = SPARSE_BYTE_INSERT(off, data);
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} else if (sz == 2) {
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new_data = SPARSE_WORD_INSERT(off, data);
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} else {
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new_data = data;
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}
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#if 0
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printf("CFGWRITE MID%d %d.%d.%d sz %d off %d paddr %lx, data %x new_data %x\n",
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mcbus_get_mid(dev), secondary, slot, func, sz, off, paddr, data, new_data);
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#endif
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*dp = new_data;
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}
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if (secondary) {
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}
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}
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static u_int8_t
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mcpcia_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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return (u_int8_t) mcpcia_cfgread(h, b, s, f, r, 1);
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}
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static u_int16_t
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mcpcia_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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return (u_int16_t) mcpcia_cfgread(h, b, s, f, r, 2);
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}
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static u_int32_t
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mcpcia_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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return mcpcia_cfgread(h, b, s, f, r, 4);
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}
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static void
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mcpcia_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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mcpcia_cfgwrite(h, b, s, f, r, 1, (u_int32_t) data);
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}
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static void
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mcpcia_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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mcpcia_cfgwrite(h, b, s, f, r, 2, (u_int32_t) data);
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}
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static void
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mcpcia_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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mcpcia_cfgwrite(h, b, s, f, r, 4, (u_int32_t) data);
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}
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static int
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mcpcia_probe(device_t dev)
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{
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device_t child;
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int unit;
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struct mcpcia_softc *xc, *sc = MCPCIA_SOFTC(dev);
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unit = device_get_unit(dev);
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if (mcpcias[unit]) {
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printf("%s: already attached\n", device_get_nameunit(dev));
|
|
return EEXIST;
|
|
}
|
|
sc->mcpcia_inst = unit;
|
|
if ((xc = mcpcia_root) == NULL) {
|
|
mcpcia_root = sc;
|
|
} else {
|
|
while (xc->next)
|
|
xc = xc->next;
|
|
xc->next = sc;
|
|
}
|
|
sc->dev = mcpcias[unit] = dev;
|
|
/* PROBE ? */
|
|
device_set_desc(dev, "MCPCIA PCI Adapter");
|
|
if (unit == 0) {
|
|
pci_init_resources();
|
|
}
|
|
child = device_add_child(dev, "pcib", unit);
|
|
device_set_ivars(child, &sc->mcpcia_inst);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mcpcia_attach(device_t dev)
|
|
{
|
|
struct mcpcia_softc *sc = MCPCIA_SOFTC(dev);
|
|
device_t p = device_get_parent(dev);
|
|
vm_offset_t regs;
|
|
u_int32_t ctl;
|
|
int mid, gid, rval;
|
|
void *intr;
|
|
|
|
chipset = mcpcia_chipset;
|
|
mid = mcbus_get_mid(dev);
|
|
gid = mcbus_get_gid(dev);
|
|
|
|
sc->sysbase = MCBUS_IOSPACE |
|
|
(((u_int64_t) gid) << MCBUS_GID_SHIFT) | \
|
|
(((u_int64_t) mid) << MCBUS_MID_SHIFT);
|
|
regs = (vm_offset_t) KV(sc->sysbase);
|
|
sc->dmem_base = regs + MCPCIA_PCI_DENSE;
|
|
sc->smem_base = regs + MCPCIA_PCI_SPARSE;
|
|
sc->io_base = regs + MCPCIA_PCI_IOSPACE;
|
|
|
|
/*
|
|
* Disable interrupts and clear errors prior to probing
|
|
*/
|
|
REGVAL(MCPCIA_INT_MASK0(sc)) = 0;
|
|
REGVAL(MCPCIA_INT_MASK1(sc)) = 0;
|
|
REGVAL(MCPCIA_CAP_ERR(sc)) = 0xFFFFFFFF;
|
|
alpha_mb();
|
|
|
|
|
|
/*
|
|
* Say who we are
|
|
*/
|
|
ctl = REGVAL(MCPCIA_PCI_REV(sc));
|
|
printf("%s: Horse Revision %d, %s Handed Saddle Revision %d,"
|
|
" CAP Revision %d\n", device_get_nameunit(dev), HORSE_REV(ctl),
|
|
(SADDLE_TYPE(ctl) & 1)? "Right": "Left", SADDLE_REV(ctl),
|
|
CAP_REV(ctl));
|
|
|
|
/*
|
|
* See if we're the fella with the EISA bus...
|
|
*/
|
|
|
|
if (EISA_PRESENT(REGVAL(MCPCIA_PCI_REV(sc)))) {
|
|
mcpcia_eisa = sc;
|
|
}
|
|
|
|
/*
|
|
* Set up DMA stuff here.
|
|
*/
|
|
|
|
mcpcia_dma_init(sc);
|
|
|
|
/*
|
|
* Register our interrupt service requirements with out parent.
|
|
*/
|
|
rval =
|
|
BUS_SETUP_INTR(p, dev, NULL, INTR_TYPE_MISC, mcpcia_intr, 0, &intr);
|
|
if (rval == 0) {
|
|
bus_generic_attach(dev);
|
|
}
|
|
return (rval);
|
|
}
|
|
|
|
static void mcpcia_enable_intr(struct mcpcia_softc *, int);
|
|
static void mcpcia_disable_intr(struct mcpcia_softc *, int);
|
|
|
|
void
|
|
mcpcia_enable_intr(struct mcpcia_softc *sc, int irq)
|
|
{
|
|
alpha_mb();
|
|
REGVAL(MCPCIA_INT_MASK0(sc)) |= (1 << irq);
|
|
alpha_mb();
|
|
}
|
|
|
|
void
|
|
mcpcia_disable_intr(struct mcpcia_softc *sc, int irq)
|
|
{
|
|
alpha_mb();
|
|
REGVAL(MCPCIA_INT_MASK0(sc)) &= ~(1 << irq);
|
|
alpha_mb();
|
|
}
|
|
|
|
static int
|
|
mcpcia_setup_intr(device_t dev, device_t child, struct resource *ir, int flags,
|
|
driver_intr_t *intr, void *arg, void **cp)
|
|
{
|
|
struct mcpcia_softc *sc = MCPCIA_SOFTC(dev);
|
|
int slot, mid, gid, birq, irq, error, intpin, h;
|
|
|
|
intpin = pci_get_intpin(child);
|
|
if (intpin == 0) {
|
|
/* No IRQ used */
|
|
return (0);
|
|
}
|
|
if (intpin < 1 || intpin > 4) {
|
|
/* Bad IRQ */
|
|
return (ENXIO);
|
|
}
|
|
|
|
slot = pci_get_slot(child);
|
|
mid = mcbus_get_mid(dev);
|
|
gid = mcbus_get_gid(dev);
|
|
|
|
if (mid == 5 && slot == 1) {
|
|
irq = 16; /* MID 5, slot 1, is the internal NCR 53c810 */
|
|
} else if (slot >= 2 && slot <= 5) {
|
|
irq = (slot - 2) * 4;
|
|
} else {
|
|
device_printf(child, "wierd slot number (%d); can't make irq\n",
|
|
slot);
|
|
return (ENXIO);
|
|
}
|
|
error = rman_activate_resource(ir);
|
|
if (error)
|
|
return error;
|
|
|
|
/*
|
|
* We now construct a vector as the hardware would, unless
|
|
* this is the internal NCR 53c810 interrupt.
|
|
*/
|
|
if (irq == 16) {
|
|
h = MCPCIA_VEC_NCR;
|
|
} else {
|
|
h = MCPCIA_VEC_PCI + ((mid - 4) * MCPCIA_VECWIDTH_PER_MCPCIA) +
|
|
(slot * MCPCIA_VECWIDTH_PER_SLOT) +
|
|
((intpin - 1) * MCPCIA_VECWIDTH_PER_INTPIN);
|
|
}
|
|
birq = irq + INTRCNT_KN300_IRQ;
|
|
error = alpha_setup_intr(h, intr, arg, cp, &intrcnt[birq]);
|
|
if (error)
|
|
return error;
|
|
mcpcia_enable_intr(sc, irq);
|
|
device_printf(child, "interrupting at IRQ 0x%x INT%c (vec 0x%x)\n",
|
|
irq, intpin - 1 + 'A' , h);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
mcpcia_teardown_intr(device_t dev, device_t child, struct resource *i, void *c)
|
|
{
|
|
struct mcpcia_softc *sc = MCPCIA_SOFTC(dev);
|
|
int slot, mid, irq;
|
|
|
|
slot = pci_get_slot(child);
|
|
mid = mcbus_get_mid(dev);
|
|
|
|
if (mid == 5 && slot == 1) {
|
|
irq = 16;
|
|
} else if (slot >= 2 && slot <= 5) {
|
|
irq = (slot - 2) * 4;
|
|
} else {
|
|
return (ENXIO);
|
|
}
|
|
mcpcia_disable_intr(sc, irq);
|
|
alpha_teardown_intr(c);
|
|
return (rman_deactivate_resource(i));
|
|
}
|
|
|
|
static void
|
|
mcpcia_sgmap_map(void *arg, vm_offset_t ba, vm_offset_t pa)
|
|
{
|
|
u_int64_t *sgtable = arg;
|
|
int index = alpha_btop(ba - MCPCIA_ISA_SG_MAPPED_BASE);
|
|
|
|
if (pa) {
|
|
if (pa > (1L<<32))
|
|
panic("mcpcia_sgmap_map: can't map address 0x%lx", pa);
|
|
sgtable[index] = ((pa >> 13) << 1) | 1;
|
|
} else {
|
|
sgtable[index] = 0;
|
|
}
|
|
alpha_mb();
|
|
MCPCIA_SGTLB_INVALIDATE(mcpcia_eisa);
|
|
}
|
|
|
|
static void
|
|
mcpcia_dma_init(struct mcpcia_softc *sc)
|
|
{
|
|
|
|
/*
|
|
* Disable all windows first.
|
|
*/
|
|
|
|
REGVAL(MCPCIA_W0_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_W1_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_W2_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_W3_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_T0_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_T1_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_T2_BASE(sc)) = 0;
|
|
REGVAL(MCPCIA_T3_BASE(sc)) = 0;
|
|
alpha_mb();
|
|
|
|
/*
|
|
* Set up window 0 as an 8MB SGMAP-mapped window starting at 8MB.
|
|
* Do this only for the EISA carrying MCPCIA. Partly because
|
|
* there's only one chipset sgmap thingie.
|
|
*/
|
|
|
|
if (sc == mcpcia_eisa) {
|
|
void *sgtable;
|
|
REGVAL(MCPCIA_W0_MASK(sc)) = MCPCIA_WMASK_8M;
|
|
|
|
sgtable = contigmalloc(8192, M_DEVBUF,
|
|
M_NOWAIT, 0, 1L<<34, 32<<10, 1L<<34);
|
|
|
|
if (sgtable == NULL) {
|
|
panic("mcpcia_dma_init: cannot allocate sgmap");
|
|
/* NOTREACHED */
|
|
}
|
|
REGVAL(MCPCIA_T0_BASE(sc)) =
|
|
pmap_kextract((vm_offset_t)sgtable) >> MCPCIA_TBASEX_SHIFT;
|
|
|
|
alpha_mb();
|
|
REGVAL(MCPCIA_W0_BASE(sc)) = MCPCIA_WBASE_EN |
|
|
MCPCIA_WBASE_SG | MCPCIA_ISA_SG_MAPPED_BASE;
|
|
alpha_mb();
|
|
MCPCIA_SGTLB_INVALIDATE(sc);
|
|
chipset.sgmap = sgmap_map_create(MCPCIA_ISA_SG_MAPPED_BASE,
|
|
MCPCIA_ISA_SG_MAPPED_BASE + MCPCIA_ISA_SG_MAPPED_SIZE - 1,
|
|
mcpcia_sgmap_map, sgtable);
|
|
}
|
|
|
|
/*
|
|
* Set up window 1 as a 2 GB Direct-mapped window starting at 2GB.
|
|
*/
|
|
|
|
REGVAL(MCPCIA_W1_MASK(sc)) = MCPCIA_WMASK_2G;
|
|
REGVAL(MCPCIA_T1_BASE(sc)) = 0;
|
|
alpha_mb();
|
|
REGVAL(MCPCIA_W1_BASE(sc)) =
|
|
MCPCIA_DIRECT_MAPPED_BASE | MCPCIA_WBASE_EN;
|
|
alpha_mb();
|
|
|
|
/*
|
|
* When we get around to redoing the 'chipset' stuff to have more
|
|
* than one sgmap handler...
|
|
*/
|
|
|
|
#if 0
|
|
/*
|
|
* Set up window 2 as a 1G SGMAP-mapped window starting at 1G.
|
|
*/
|
|
|
|
REGVAL(MCPCIA_W2_MASK(sc)) = MCPCIA_WMASK_1G;
|
|
REGVAL(MCPCIA_T2_BASE(sc)) =
|
|
ccp->cc_pci_sgmap.aps_ptpa >> MCPCIA_TBASEX_SHIFT;
|
|
alpha_mb();
|
|
REGVAL(MCPCIA_W2_BASE(sc)) =
|
|
MCPCIA_WBASE_EN | MCPCIA_WBASE_SG | MCPCIA_PCI_SG_MAPPED_BASE;
|
|
alpha_mb();
|
|
#endif
|
|
|
|
/* XXX XXX BEGIN XXX XXX */
|
|
{ /* XXX */
|
|
alpha_XXX_dmamap_or = MCPCIA_DIRECT_MAPPED_BASE;/* XXX */
|
|
} /* XXX */
|
|
/* XXX XXX END XXX XXX */
|
|
}
|
|
|
|
/*
|
|
*/
|
|
|
|
static void
|
|
mcpcia_intr(void *arg)
|
|
{
|
|
unsigned long vec = (unsigned long) arg;
|
|
|
|
if (vec >= MCPCIA_VEC_EISA && vec < MCPCIA_VEC_PCI) {
|
|
#if NSIO > 0
|
|
sio_iointr(framep, vec);
|
|
return;
|
|
#else
|
|
panic("mcpcia_intr: (E)ISA interrupt support not configured "
|
|
"for vector 0x%lx", vec);
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Check for I2C interrupts. These are technically within
|
|
* the PCI vector range, but no PCI device should ever map
|
|
* to them.
|
|
*/
|
|
if (vec == MCPCIA_I2C_CVEC) {
|
|
printf("i2c: controller interrupt\n");
|
|
return;
|
|
}
|
|
if (vec == MCPCIA_I2C_BVEC) {
|
|
printf("i2c: bus interrupt\n");
|
|
return;
|
|
}
|
|
|
|
alpha_dispatch_intr(NULL, vec);
|
|
}
|
|
DRIVER_MODULE(mcpcia, mcbus, mcpcia_driver, mcpcia_devclass, 0, 0);
|