2897614119
Peter Wemm <peter@spinner.DIALix.COM>, Steve Passe <smp@csn.net> removed all the IPI_INTS code. made the XFAST_IPI32 code default, renaming Xfastipi32 to Xinvltlb.
340 lines
8.0 KiB
C
340 lines
8.0 KiB
C
/*
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* Copyright (c) 1996, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: mpapic.h,v 1.1 1997/04/26 11:45:38 peter Exp $
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*/
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#ifndef _MACHINE_MPAPIC_H_
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#define _MACHINE_MPAPIC_H_
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#include <i386/isa/icu.h>
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#include <i386/include/apic.h>
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/* number of busses */
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#if !defined(NBUS)
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# define NBUS 4
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#endif /* NBUS */
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/* total number of APIC INTs, including SHARED INTs */
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#if !defined(NINTR)
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#define NINTR 24
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#endif /* NINTR */
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/* size of APIC ID list */
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#define NAPICID 16
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/* number of IO APICs */
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# if !defined(NAPIC)
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# define NAPIC 1
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# endif /* NAPIC */
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/* use inline xxxIPI functions */
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#define FAST_IPI_NOT
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#define APICIPI_BANDAID
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/* these don't really belong in here... */
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enum busTypes {
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CBUS = 1,
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CBUSII = 2,
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EISA = 3,
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ISA = 6,
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PCI = 13,
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XPRESS = 18,
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MAX_BUSTYPE = 18,
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UNKNOWN_BUSTYPE = 0xff
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};
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/*
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* the physical/logical APIC ID management macors
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*/
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#define CPU_TO_ID(CPU) (cpu_num_to_apic_id[CPU])
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#define ID_TO_CPU(ID) (apic_id_to_logical[ID])
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#define IO_TO_ID(IO) (io_num_to_apic_id[IO])
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#define ID_TO_IO(ID) (apic_id_to_logical[ID])
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/*
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* inline functions to read/write the IO APIC
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* NOTES:
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* unlike the local APIC, the IO APIC is accessed indirectly thru 2 registers.
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* the select register is loaded with an index to the desired 'window' reg.
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* the 'window' is accessed as a 32 bit unsigned.
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*/
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/*
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* read 'reg' from 'apic'
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*/
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#if defined(MULTIPLE_IOAPICS)
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#error MULTIPLE_IOAPICSXXX
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#else
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static __inline u_int32_t
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io_apic_read(int apic __attribute__ ((unused)), int reg)
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{
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(*io_apic_base) = reg;
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return (*(io_apic_base + (IOAPIC_WINDOW / sizeof(u_int))));
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}
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#endif /* MULTIPLE_IOAPICS */
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/*
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* write 'value' to 'reg' of 'apic'
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*/
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#if defined(MULTIPLE_IOAPICS)
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#error MULTIPLE_IOAPICSXXX
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#else
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static __inline void
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io_apic_write(int apic __attribute__ ((unused)), int reg, u_int32_t value)
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{
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(*io_apic_base) = reg;
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(*(io_apic_base + (IOAPIC_WINDOW / sizeof(u_int)))) = value;
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}
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#endif /* MULTIPLE_IOAPICS */
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#if defined(READY)
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/*
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* set the IO APIC mask for INT# 'i'
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*/
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#if defined(MULTIPLE_IOAPICS)
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#error MULTIPLE_IOAPICSXXX
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#else
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static __inline void
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set_io_apic_mask(int apic, u_int32_t i)
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{
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int select; /* the select register is 8 bits */
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u_int32_t low_reg; /* the window register is 32 bits */
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imen |= (1<<i); /* set mask variable */
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select = IOAPIC_REDTBL + (i * 2); /* calculate addr */
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low_reg = io_apic_read(select); /* read contents */
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low_reg |= IOART_INTMASK; /* set mask */
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io_apic_write(select, low_reg); /* new value */
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}
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#endif /* MULTIPLE_IOAPICS */
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#endif /* READY */
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#if defined(READY)
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/*
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* clear the IO APIC mask for INT# 'i'
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*/
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#if defined(MULTIPLE_IOAPICS)
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#error MULTIPLE_IOAPICSXXX
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#else
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static __inline void
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clr_io_apic_mask(int apic, u_int32_t i)
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{
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int select; /* the select register is 8 bits */
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u_int32_t low_reg; /* the window register is 32 bits */
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imen &= ~(1<<i); /* clear mask variable */
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select = IOAPIC_REDTBL + (i * 2); /* calculate addr */
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low_reg = io_apic_read(select); /* read contents */
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low_reg &= ~IOART_INTMASK; /* clear mask */
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io_apic_write(select, low_reg); /* new value */
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}
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#endif /* MULTIPLE_IOAPICS */
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#endif /* READY */
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/*
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* read current IRQ0 -IRQ23 masks
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*/
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#if defined(MULTIPLE_IOAPICS)
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#error MULTIPLE_IOAPICSXXX
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#else
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static __inline u_int32_t
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read_io_apic_mask24(int apic __attribute__ ((unused)))
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{
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return (imen & 0x00ffffff); /* return our global copy */
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}
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#endif /* MULTIPLE_IOAPICS */
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/*
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* send an EndOfInterrupt to the local APIC
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*/
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static __inline void
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apic_eoi(void)
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{
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apic_base[APIC_EOI] = 0;
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}
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#if defined(FAST_IPI)
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/*
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* send APIC IPI 'vector' to 'destType' via 'deliveryMode'
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*
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* destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
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* vector is any valid SYSTEM INT vector
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* deliveryMode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
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*/
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static __inline int
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apic_ipi(int destType, int vector, int deliveryMode)
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{
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u_long icr_lo;
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/* build IRC_LOW */
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icr_lo = (apic_base[APIC_ICR_LOW] & APIC_RESV2_MASK) |
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destType | deliveryMode | vector;
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/* write APIC ICR */
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apic_base[APIC_ICR_LOW] = icr_lo;
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/* wait for pending status end */
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while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
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/* spin */ ;
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/** FIXME: return result */
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return 0;
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}
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/*
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* send an IPI INTerrupt containing 'vector' to CPU 'target'
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* NOTE: target is a LOGICAL APIC ID
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*/
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static __inline int
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selected_proc_ipi(int target, int vector)
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{
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u_long icr_lo;
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u_long icr_hi;
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/* write the destination field for the target AP */
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icr_hi = (apic_base[APIC_ICR_HI] & ~APIC_ID_MASK) |
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(cpu_num_to_apic_id[target] << 24);
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apic_base[APIC_ICR_HI] = icr_hi;
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/* write command */
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icr_lo = (apic_base[APIC_ICR_LOW] & APIC_RESV2_MASK) |
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APIC_DEST_DESTFLD | APIC_DELMODE_FIXED | vector;
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apic_base[APIC_ICR_LOW] = icr_lo;
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/* wait for pending status end */
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while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
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/* spin */ ;
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return 0; /** FIXME: return result */
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}
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/*
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* send an IPI INTerrupt containing 'vector' to CPUs in 'targetMap'
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* 'targetMap' is a bitfiled of length 14,
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* APIC #0 == bit 0, ..., APIC #14 == bit 14
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* NOTE: these are LOGICAL APIC IDs
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*/
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static __inline int
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selected_procs_ipi(int targetMap, int vector)
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{
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return selected_apic_ipi(targetMap, vector, APIC_DELMODE_FIXED);
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}
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/*
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* send an IPI INTerrupt containing 'vector' to all CPUs, including myself
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*/
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static __inline int
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all_procs_ipi(int vector)
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{
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u_int32_t icr_lo;
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/* build command */
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icr_lo = (apic_base[APIC_ICR_LOW] & APIC_RESV2_MASK) |
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APIC_DEST_ALLISELF | APIC_DELMODE_FIXED | vector;
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/* write command */
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apic_base[APIC_ICR_LOW] = icr_lo;
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/* wait for pending status end */
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while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
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/* spin */ ;
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return 0; /** FIXME: return result */
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}
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/*
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* send an IPI INTerrupt containing 'vector' to all CPUs EXCEPT myself
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*/
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static __inline int
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all_but_self_ipi(int vector)
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{
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u_int32_t icr_lo;
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/* build command */
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icr_lo = (apic_base[APIC_ICR_LOW] & APIC_RESV2_MASK) |
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APIC_DEST_ALLESELF | APIC_DELMODE_FIXED | vector;
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/* write command */
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apic_base[APIC_ICR_LOW] = icr_lo;
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/* wait for pending status end */
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while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
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/* spin */ ;
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return 0; /** FIXME: return result */
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}
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/*
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* send an IPI INTerrupt containing 'vector' to myself
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*/
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static __inline int
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self_ipi(int vector)
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{
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u_int32_t icr_lo;
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/* build command */
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icr_lo = (apic_base[APIC_ICR_LOW] & APIC_RESV2_MASK) |
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APIC_DEST_SELF | APIC_DELMODE_FIXED | vector;
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/* write command */
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apic_base[APIC_ICR_LOW] = icr_lo;
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/* wait for pending status end */
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while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK)
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/* spin */ ;
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return 0; /** FIXME: return result */
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}
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# else /* !FAST_IPI */
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int apic_ipi __P((int, int, int));
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int selected_procs_ipi __P((int, int));
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int all_procs_ipi __P((int));
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int all_but_self_ipi __P((int));
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int self_ipi __P((int));
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#endif /* FAST_IPI */
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#endif /* _MACHINE_MPAPIC_H */
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