200 lines
4.4 KiB
ArmAsm
200 lines
4.4 KiB
ArmAsm
/*-
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* Copyright (c) 1997, by Steve Passe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: apic_ipl.s,v 1.2 1997/07/20 18:11:45 smp Exp smp $
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*/
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#include <machine/smptests.h> /** NEW_STRATEGY, APIC_PIN0_TIMER */
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.data
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ALIGN_DATA
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#ifdef NEW_STRATEGY
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/* this allows us to change the 8254 APIC pin# assignment */
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.globl _Xintr8254
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_Xintr8254:
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.long _Xintr7
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/* used by this file, microtime.s and clock.c */
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.globl _mask8254
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_mask8254:
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.long 0
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#else /** NEW_STRATEGY */
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#ifndef APIC_PIN0_TIMER
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/* this allows us to change the 8254 APIC pin# assignment */
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.globl _Xintr8254
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_Xintr8254:
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.long _Xintr7
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/* used by this file, microtime.s and clock.c */
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.globl _mask8254
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_mask8254:
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.long 0
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#endif /* APIC_PIN0_TIMER */
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#endif /** NEW_STRATEGY */
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/* */
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.globl _vec
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_vec:
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.long vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7
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.long vec8, vec9, vec10, vec11, vec12, vec13, vec14, vec15
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.long vec16, vec17, vec18, vec19, vec20, vec21, vec22, vec23
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/*
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*
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*/
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.text
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SUPERALIGN_TEXT
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/*
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* Fake clock interrupt(s) so that they appear to come from our caller instead
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* of from here, so that system profiling works.
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* XXX do this more generally (for all vectors; look up the C entry point).
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* XXX frame bogusness stops us from just jumping to the C entry point.
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*/
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/*
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* generic vector function for 8254 clock
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*/
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ALIGN_TEXT
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#ifdef NEW_STRATEGY
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.globl _vec8254
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_vec8254:
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popl %eax /* return address */
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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movl _mask8254, %eax /* lazy masking */
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notl %eax
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andl %eax, iactive
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MEXITCOUNT
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movl _Xintr8254, %eax
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jmp %eax /* XXX might need _Xfastintr# */
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#else /** NEW_STRATEGY */
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#ifdef APIC_PIN0_TIMER
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vec0:
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popl %eax /* return address */
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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andl $~IRQ_BIT(0), iactive ; /* lazy masking */
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MEXITCOUNT
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jmp _Xintr0 /* XXX might need _Xfastintr0 */
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#else
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.globl _vec8254
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_vec8254:
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popl %eax /* return address */
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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movl _mask8254, %eax /* lazy masking */
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notl %eax
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andl %eax, iactive
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MEXITCOUNT
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movl _Xintr8254, %eax
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jmp %eax /* XXX might need _Xfastintr# */
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#endif /* APIC_PIN0_TIMER */
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#endif /** NEW_STRATEGY */
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/*
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* generic vector function for RTC clock
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*/
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ALIGN_TEXT
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vec8:
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popl %eax
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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andl $~IRQ_BIT(8), iactive ; /* lazy masking */
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MEXITCOUNT
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jmp _Xintr8 /* XXX might need _Xfastintr8 */
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/*
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* The 'generic' vector stubs.
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*/
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#define BUILD_VEC(irq_num) \
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ALIGN_TEXT ; \
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__CONCAT(vec,irq_num): ; \
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popl %eax ; \
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pushfl ; \
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pushl $KCSEL ; \
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pushl %eax ; \
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cli ; \
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andl $~IRQ_BIT(irq_num), iactive ; /* lazy masking */ \
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MEXITCOUNT ; \
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jmp __CONCAT(_Xintr,irq_num)
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#ifdef NEW_STRATEGY
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BUILD_VEC(0)
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#else /** NEW_STRATEGY */
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#ifndef APIC_PIN0_TIMER
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BUILD_VEC(0)
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#endif /* APIC_PIN0_TIMER */
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#endif /** NEW_STRATEGY */
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BUILD_VEC(1)
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BUILD_VEC(2)
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BUILD_VEC(3)
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BUILD_VEC(4)
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BUILD_VEC(5)
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BUILD_VEC(6)
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BUILD_VEC(7)
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/* IRQ8 is special case, done above */
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BUILD_VEC(9)
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BUILD_VEC(10)
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BUILD_VEC(11)
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BUILD_VEC(12)
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BUILD_VEC(13)
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BUILD_VEC(14)
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BUILD_VEC(15)
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BUILD_VEC(16) /* 8 additional INTs in IO APIC */
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BUILD_VEC(17)
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BUILD_VEC(18)
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BUILD_VEC(19)
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BUILD_VEC(20)
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BUILD_VEC(21)
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BUILD_VEC(22)
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BUILD_VEC(23)
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