302 lines
9.8 KiB
C
302 lines
9.8 KiB
C
/*
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* Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* 4. Altered versions must be plainly marked as such, and must not be
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* misrepresented as being the original software and/or documentation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* $Id: i4b_hscx.h,v 1.4 1999/02/14 09:44:59 hm Exp $
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*
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* last edit-date: [Sun Feb 14 10:26:56 1999]
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*
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* -hm added AVM config register defs
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* -hm split up for rewrite of Siemens chipset driver
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*
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*---------------------------------------------------------------------------
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*/
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#ifndef I4B_HSCX_H_
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#define I4B_HSCX_H_
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enum HSCX_VERSIONS {
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HSCX_VA1, /* 82525 A1 */
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HSCX_UNKN1, /* unknown 1 */
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HSCX_VA2, /* 82525 A2 */
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HSCX_UNKN3, /* unknown 3 */
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HSCX_VA3, /* 82525 A3 */
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HSCX_V21, /* 82525 2.1 */
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HSCX_UNKN /* unknown version */
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};
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#define HSCX_CH_A 0 /* channel A */
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#define HSCX_CH_B 1 /* channel B */
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#define HSCX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
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/*
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* definitions of registers and bits for the HSCX ISDN chip.
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*/
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typedef struct hscx_reg {
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/* 32 byte deep FIFO always first */
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unsigned char hscx_fifo [HSCX_FIFO_LEN];
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/* most registers can be read/written, but have different names */
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/* so define a union with read/write names to make that clear */
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union {
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struct {
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unsigned char hscx_ista;
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unsigned char hscx_star;
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unsigned char hscx_mode;
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unsigned char hscx_timr;
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unsigned char hscx_exir;
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unsigned char hscx_rbcl;
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unsigned char dummy_26;
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unsigned char hscx_rsta;
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unsigned char hscx_ral1;
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unsigned char hscx_rhcr;
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unsigned char dummy_2a;
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unsigned char dummy_2b;
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unsigned char hscx_ccr2;
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unsigned char hscx_rbch;
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unsigned char hscx_vstr;
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unsigned char hscx_ccr;
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unsigned char dummy_30;
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unsigned char dummy_31;
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unsigned char dummy_32;
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unsigned char dummy_33;
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} hscx_r;
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struct {
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unsigned char hscx_mask;
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unsigned char hscx_cmdr;
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unsigned char hscx_mode;
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unsigned char hscx_timr;
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unsigned char hscx_xad1;
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unsigned char hscx_xad2;
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unsigned char hscx_rah1;
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unsigned char hscx_rah2;
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unsigned char hscx_ral1;
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unsigned char hscx_ral2;
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unsigned char hscx_xbcl;
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unsigned char hscx_bgr;
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unsigned char hscx_ccr2;
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unsigned char hscx_xbch;
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unsigned char hscx_rlcr;
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unsigned char hscx_ccr1;
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unsigned char hscx_tsax;
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unsigned char hscx_tsar;
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unsigned char hscx_xccr;
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unsigned char hscx_rccr;
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} hscx_w;
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} hscx_rw;
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} hscx_reg_t;
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#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
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/* HSCX read registers */
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#define h_ista hscx_rw.hscx_r.hscx_ista
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#define H_ISTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ista)
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#define h_star hscx_rw.hscx_r.hscx_star
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#define H_STAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_star)
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#define h_mode hscx_rw.hscx_r.hscx_mode
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#define H_MODE REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_mode)
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#define h_timr hscx_rw.hscx_r.hscx_timr
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#define H_TIMR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_timr)
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#define h_exir hscx_rw.hscx_r.hscx_exir
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#define H_EXIR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_exir)
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#define h_rbcl hscx_rw.hscx_r.hscx_rbcl
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#define H_RBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbcl)
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#define h_rsta hscx_rw.hscx_r.hscx_rsta
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#define H_RSTA REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rsta)
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#define h_ral1 hscx_rw.hscx_r.hscx_ral1
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#define H_RAL1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ral1)
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#define h_rhcr hscx_rw.hscx_r.hscx_rhcr
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#define H_RHCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rhcr)
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#define h_ccr2 hscx_rw.hscx_r.hscx_ccr2
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#define H_CCR2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr2)
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#define h_rbch hscx_rw.hscx_r.hscx_rbch
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#define H_RBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_rbch)
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#define h_vstr hscx_rw.hscx_r.hscx_vstr
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#define H_VSTR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_vstr)
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#define h_ccr hscx_rw.hscx_r.hscx_ccr
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#define H_CCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_r.hscx_ccr)
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/* HSCX write registers - for hscx_mode, hscx_timr, hscx_ral1, hscx_ccr2 */
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/* see read registers */
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#define h_mask hscx_rw.hscx_w.hscx_mask
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#define H_MASK REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_mask)
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#define h_cmdr hscx_rw.hscx_w.hscx_cmdr
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#define H_CMDR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_cmdr)
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#define h_xad1 hscx_rw.hscx_w.hscx_xad1
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#define H_XAD1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad1)
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#define h_xad2 hscx_rw.hscx_w.hscx_xad2
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#define H_XAD2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xad2)
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#define h_rah1 hscx_rw.hscx_w.hscx_rah1
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#define H_RAH1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah1)
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#define h_rah2 hscx_rw.hscx_w.hscx_rah2
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#define H_RAH2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rah2)
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#define h_ral2 hscx_rw.hscx_w.hscx_ral2
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#define H_RAL2 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ral2)
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#define h_xbcl hscx_rw.hscx_w.hscx_xbcl
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#define H_XBCL REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbcl)
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#define h_bgr hscx_rw.hscx_w.hscx_bgr
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#define H_BGR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_bgr)
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#define h_xbch hscx_rw.hscx_w.hscx_xbch
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#define H_XBCH REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xbch)
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#define h_rlcr hscx_rw.hscx_w.hscx_rlcr
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#define H_RLCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rlcr)
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#define h_ccr1 hscx_rw.hscx_w.hscx_ccr1
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#define H_CCR1 REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_ccr1)
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#define h_tsax hscx_rw.hscx_w.hscx_tsax
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#define H_TSAX REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsax)
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#define h_tsar hscx_rw.hscx_w.hscx_tsar
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#define H_TSAR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_tsar)
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#define h_xccr hscx_rw.hscx_w.hscx_xccr
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#define H_XCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_xccr)
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#define h_rccr hscx_rw.hscx_w.hscx_rccr
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#define H_RCCR REG_OFFSET(hscx_reg_t, hscx_rw.hscx_w.hscx_rccr)
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#define HSCX_ISTA_RME 0x80
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#define HSCX_ISTA_RPF 0x40
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#define HSCX_ISTA_RSC 0x20
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#define HSCX_ISTA_XPR 0x10
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#define HSCX_ISTA_TIN 0x08
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#define HSCX_ISTA_ICA 0x04
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#define HSCX_ISTA_EXA 0x02
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#define HSCX_ISTA_EXB 0x01
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#define HSCX_MASK_RME 0x80
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#define HSCX_MASK_RPF 0x40
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#define HSCX_MASK_RSC 0x20
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#define HSCX_MASK_XPR 0x10
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#define HSCX_MASK_TIN 0x08
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#define HSCX_MASK_ICA 0x04
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#define HSCX_MASK_EXA 0x02
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#define HSCX_MASK_EXB 0x01
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#define HSCX_EXIR_XMR 0x80
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#define HSCX_EXIR_XDU 0x40
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#define HSCX_EXIR_PCE 0x20
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#define HSCX_EXIR_RFO 0x10
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#define HSCX_EXIR_CSC 0x08
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#define HSCX_EXIR_RFS 0x04
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/* the other bits are always 0 */
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#define HSCX_STAR_XDOV 0x80
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#define HSCX_STAR_XFW 0x40
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#define HSCX_STAR_XRNR 0x20
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#define HSCX_STAR_RRNR 0x10
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#define HSCX_STAR_RLI 0x08
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#define HSCX_STAR_CEC 0x04
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#define HSCX_STAR_CTS 0x02
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#define HSCX_STAR_WFA 0x01
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#define HSCX_CMDR_RMC 0x80
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#define HSCX_CMDR_RHR 0x40
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/* also known as XREP in transparent mode */
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#define HSCX_CMDR_RNR 0x20
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#define HSCX_CMDR_STI 0x10
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#define HSCX_CMDR_XTF 0x08
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#define HSCX_CMDR_XIF 0x04
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#define HSCX_CMDR_XME 0x02
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#define HSCX_CMDR_XRES 0x01
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#define HSCX_MODE_MDS1 0x80
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#define HSCX_MODE_MDS0 0x40
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#define HSCX_MODE_ADM 0x20
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#define HSCX_MODE_TMD 0x10
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#define HSCX_MODE_RAC 0x08
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#define HSCX_MODE_RTS 0x04
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#define HSCX_MODE_TRS 0x02
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#define HSCX_MODE_TLP 0x01
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#define HSCX_RSTA_VFR 0x80
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#define HSCX_RSTA_RDO 0x40
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#define HSCX_RSTA_CRC 0x20
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#define HSCX_RSTA_RAB 0x10
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#define HSCX_RSTA_HA1 0x08
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#define HSCX_RSTA_HA0 0x04
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#define HSCX_RSTA_CR 0x02
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#define HSCX_RSTA_LA 0x01
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#define HSCX_RSTA_MASK 0xf0 /* the interesting ones */
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/* only used in DMA mode */
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#define HSCX_XBCH_DMA 0x80
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#define HSCX_XBCH_NRM 0x40
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#define HSCX_XBCH_CAS 0x20
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#define HSCX_XBCH_XC 0x10
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/* the rest are bits 11 thru 8 of the byte count */
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#define HSCX_RBCH_DMA 0x80
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#define HSCX_RBCH_NRM 0x40
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#define HSCX_RBCH_CAS 0x20
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#define HSCX_RBCH_OV 0x10
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/* the rest are bits 11 thru 8 of the byte count */
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#define HSCX_VSTR_CD 0x80
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/* bits 6 thru 4 are 0 */
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/* bits 3 thru 0 are the version number */
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#define HSCX_RLCR_RC 0x80
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/* the rest of the bits are used to set the received length */
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#define HSCX_CCR1_PU 0x80
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/* bits 6 and 5 are SC1 SC0 */
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#define HSCX_CCR1_ODS 0x10
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#define HSCX_CCR1_ITF 0x08
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#define HSCX_CCR1_CM2 0x04
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#define HSCX_CCR1_CM1 0x02
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#define HSCX_CCR1_CM0 0x01
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/* for clock mode 5 */
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#define HSCX_CCR2_SOC2 0x80
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#define HSCX_CCR2_SOC1 0x40
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#define HSCX_CCR2_XCS0 0x20
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#define HSCX_CCR2_RCS0 0x10
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#define HSCX_CCR2_TIO 0x08
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#define HSCX_CCR2_CIE 0x04
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#define HSCX_CCR2_RIE 0x02
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#define HSCX_CCR2_DIV 0x01
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/* bits 7 thru 2 are TSNX */
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#define HSCX_TSAX_XCS2 0x02
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#define HSCX_TSAX_XCS1 0x01
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/* bits 7 thru 2 are TSNR */
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#define HSCX_TSAR_RCS2 0x02
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#define HSCX_TSAR_RCS1 0x01
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#endif /* I4B_HSCX_H_ */
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