6052fa47a9
work out of the box too, but I have no hardware to test. It works well enough to go multiuser. Network works, SATA does not, as I have no drive to test. Thanks to Intel for sending such a board. Obtained from: NetBSD
329 lines
9.2 KiB
C
329 lines
9.2 KiB
C
/* $NetBSD: i80321_mainbus.c,v 1.13 2003/12/17 22:03:24 abs Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* IQ80321 front-end for the i80321 I/O Processor. We take care
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* of setting up the i80321 memory map, PCI interrupt routing, etc.,
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* which are all specific to the board the i80321 is wired up to.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#define __RMAN_RESOURCE_VISIBLE
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/xscale/i80321/i80321reg.h>
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#include <arm/xscale/i80321/i80321var.h>
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#include <arm/xscale/i80321/iq80321reg.h>
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#include <arm/xscale/i80321/iq80321var.h>
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#include <arm/xscale/i80321/i80321_intr.h>
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#include <dev/pci/pcireg.h>
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int iq80321_probe(device_t);
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void iq80321_identify(driver_t *, device_t);
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int iq80321_attach(device_t);
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int
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iq80321_probe(device_t dev)
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{
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device_set_desc(dev, "Intel 80321");
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return (0);
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}
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void
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iq80321_identify(driver_t *driver, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "iq", 0);
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}
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static struct arm32_dma_range i80321_dr;
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static int dma_range_init = 0;
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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if (dma_range_init == 0)
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return (NULL);
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return (&i80321_dr);
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}
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int
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bus_dma_get_range_nb(void)
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{
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if (dma_range_init == 0)
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return (0);
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return (1);
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}
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#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
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#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
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void pmap_kenter(vm_offset_t, vm_offset_t);
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int
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iq80321_attach(device_t dev)
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{
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struct i80321_softc *sc = device_get_softc(dev);
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int b0u, b0l, b1u, b1l;
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vm_paddr_t memstart = 0;
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vm_size_t memsize = 0;
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int busno;
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/*
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* Fill in the space tag for the i80321's own devices,
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* and hand-craft the space handle for it (the device
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* was mapped during early bootstrap).
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*/
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i80321_bs_init(&i80321_bs_tag, sc);
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sc->sc_st = &i80321_bs_tag;
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sc->sc_sh = IQ80321_80321_VBASE;
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sc->dev = dev;
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sc->sc_is_host = 1;
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/*
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* Slice off a subregion for the Memory Controller -- we need it
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* here in order read the memory size.
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*/
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE,
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VERDE_MCU_SIZE, &sc->sc_mcu_sh))
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panic("%s: unable to subregion MCU registers",
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device_get_name(dev));
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
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VERDE_ATU_SIZE, &sc->sc_atu_sh))
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panic("%s: unable to subregion ATU registers",
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device_get_name(dev));
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/*
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* We have mapped the the PCI I/O windows in the early
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* bootstrap phase.
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*/
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sc->sc_iow_vaddr = IQ80321_IOW_VBASE;
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/*
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* Check the configuration of the ATU to see if another BIOS
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* has configured us. If a PC BIOS didn't configure us, then:
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* IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c.
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* IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c.
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* If a BIOS has configured us, at least one of those should be
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* different. This is pretty fragile, but it's not clear what
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* would work better.
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*/
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b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x0);
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b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x4);
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b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0x8);
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b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCIR_MAPS+0xc);
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#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
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b0l &= PCI_MAPREG_MEM_ADDR_MASK;
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b0u &= PCI_MAPREG_MEM_ADDR_MASK;
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b1l &= PCI_MAPREG_MEM_ADDR_MASK;
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b1u &= PCI_MAPREG_MEM_ADDR_MASK;
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if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0))
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sc->sc_is_host = 0;
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else
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sc->sc_is_host = 1;
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i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize);
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/*
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* We set up the Inbound Windows as follows:
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*
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* 0 Access to i80321 PMMRs
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*
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* 1 Reserve space for private devices
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*
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* 2 RAM access
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*
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* 3 Unused.
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*
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* This chunk needs to be customized for each IOP321 application.
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*/
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#if 0
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sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE;
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sc->sc_iwin[0].iwin_base_hi = 0;
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sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE;
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sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE;
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#endif
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if (sc->sc_is_host) {
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/* Map PCI:Local 1:1. */
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sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE |
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PCI_MAPREG_MEM_PREFETCHABLE_MASK |
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PCI_MAPREG_MEM_TYPE_64BIT;
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sc->sc_iwin[1].iwin_base_hi = 0;
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} else {
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sc->sc_iwin[1].iwin_base_lo = 0;
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sc->sc_iwin[1].iwin_base_hi = 0;
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}
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sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE;
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sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE;
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if (sc->sc_is_host) {
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sc->sc_iwin[2].iwin_base_lo = memstart |
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PCI_MAPREG_MEM_PREFETCHABLE_MASK |
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PCI_MAPREG_MEM_TYPE_64BIT;
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sc->sc_iwin[2].iwin_base_hi = 0;
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} else {
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sc->sc_iwin[2].iwin_base_lo = 0;
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sc->sc_iwin[2].iwin_base_hi = 0;
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}
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sc->sc_iwin[2].iwin_xlate = memstart;
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sc->sc_iwin[2].iwin_size = memsize;
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if (sc->sc_is_host) {
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sc->sc_iwin[3].iwin_base_lo = 0 |
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PCI_MAPREG_MEM_PREFETCHABLE_MASK |
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PCI_MAPREG_MEM_TYPE_64BIT;
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} else {
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sc->sc_iwin[3].iwin_base_lo = 0;
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}
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sc->sc_iwin[3].iwin_base_hi = 0;
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sc->sc_iwin[3].iwin_xlate = 0;
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sc->sc_iwin[3].iwin_size = 0;
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/*
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* We set up the Outbound Windows as follows:
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*
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* 0 Access to private PCI space.
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*
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* 1 Unused.
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*/
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#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
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sc->sc_owin[0].owin_xlate_lo =
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PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
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sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
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/*
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* Set the Secondary Outbound I/O window to map
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* to PCI address 0 for all 64K of the I/O space.
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*/
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sc->sc_ioout_xlate = 0;
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i80321_attach(sc);
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i80321_dr.dr_sysbase = sc->sc_iwin[2].iwin_xlate;
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i80321_dr.dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
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i80321_dr.dr_len = sc->sc_iwin[2].iwin_size;
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dma_range_init = 1;
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busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
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busno = PCIXSR_BUSNO(busno);
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if (busno == 0xff)
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busno = 0;
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device_add_child(dev, "obio", 0);
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device_add_child(dev, "itimer", 0);
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device_add_child(dev, "pcib", busno);
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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return (0);
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}
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void
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arm_mask_irqs(int nb)
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{
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intr_enabled &= ~nb;
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i80321_set_intrmask();
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}
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void
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arm_unmask_irqs(int nb)
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{
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intr_enabled |= nb;
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i80321_set_intrmask();
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}
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void
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cpu_reset()
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{
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(void) disable_interrupts(I32_bit|F32_bit);
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*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
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ATU_PCSR) = PCSR_RIB | PCSR_RPB;
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printf("Reset failed :'(\n");
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for(;;);
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}
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static struct resource *
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iq80321_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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if (type == SYS_RES_IRQ) {
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struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
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res->r_start = start;
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res->r_end = end;
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return (res);
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}
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return (NULL);
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}
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static int
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iq80321_setup_intr(device_t dev, device_t child,
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struct resource *ires, int flags, driver_intr_t *intr, void *arg,
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void **cookiep)
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{
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BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, intr, arg,
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cookiep);
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intr_enabled |= 1 << ires->r_start;
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i80321_set_intrmask();
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return (0);
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}
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static device_method_t iq80321_methods[] = {
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DEVMETHOD(device_probe, iq80321_probe),
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DEVMETHOD(device_attach, iq80321_attach),
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DEVMETHOD(device_identify, iq80321_identify),
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DEVMETHOD(bus_alloc_resource, iq80321_alloc_resource),
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DEVMETHOD(bus_setup_intr, iq80321_setup_intr),
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{0, 0},
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};
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static driver_t iq80321_driver = {
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"iq",
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iq80321_methods,
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sizeof(struct i80321_softc),
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};
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static devclass_t iq80321_devclass;
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DRIVER_MODULE(iq, nexus, iq80321_driver, iq80321_devclass, 0, 0);
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