freebsd-dev/sys/x86/include
Konstantin Belousov 17edf152e5 Control for Special Register Buffer Data Sampling mitigation.
New microcode update for Intel enables mitigation for SRBDS, which
slows down RDSEED and related instructions.  The update also provides
a control to limit the mitigation to SGX enclaves, which should
restore the speed of random generator by the cost of potential
cross-core bufer sampling.

See https://software.intel.com/security-software-guidance/insights/deep-dive-special-register-buffer-data-sampling

GIve the user control over it.

Reviewed by:	markj
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
Differential revision:	https://reviews.freebsd.org/D25221
2020-06-12 22:14:45 +00:00
..
xen
_align.h
_inttypes.h
_limits.h
_stdint.h
_types.h
acpica_machdep.h
apicreg.h
apicvar.h
apm_bios.h
bus_dma.h
bus.h
busdma_impl.h
cputypes.h
dump.h
elf.h
endian.h
fdt.h
float.h
fpu.h
frame.h
ifunc.h
init.h
intr_machdep.h
legacyvar.h
mca.h
metadata.h
mptable.h
ofw_machdep.h
pci_cfgreg.h
procctl.h
psl.h
ptrace.h
pvclock.h
reg.h
segments.h
setjmp.h
sigframe.h
signal.h
specialreg.h x86: add bits definitions for SRBDS mitigation control. 2020-06-12 22:12:57 +00:00
stack.h
stdarg.h
sysarch.h
trap.h
ucode.h
ucontext.h
vdso.h
vmware.h
x86_smp.h amd64 pmap: reorder IPI send and local TLB flush in TLB invalidations. 2020-06-10 22:07:57 +00:00
x86_var.h Control for Special Register Buffer Data Sampling mitigation. 2020-06-12 22:14:45 +00:00