264 lines
12 KiB
C++
264 lines
12 KiB
C++
//===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the interface of a single recognizable instruction.
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// Documentation for the disassembler emitter in general can be found in
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// X86DisasemblerEmitter.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86RECOGNIZABLEINSTR_H
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#define X86RECOGNIZABLEINSTR_H
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#include "X86DisassemblerTables.h"
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#include "CodeGenTarget.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/ADT/SmallVector.h"
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namespace llvm {
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namespace X86Disassembler {
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/// RecognizableInstr - Encapsulates all information required to decode a single
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/// instruction, as extracted from the LLVM instruction tables. Has methods
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/// to interpret the information available in the LLVM tables, and to emit the
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/// instruction into DisassemblerTables.
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class RecognizableInstr {
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private:
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/// The opcode of the instruction, as used in an MCInst
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InstrUID UID;
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/// The record from the .td files corresponding to this instruction
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const Record* Rec;
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/// The prefix field from the record
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uint8_t Prefix;
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/// The opcode field from the record; this is the opcode used in the Intel
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/// encoding and therefore distinct from the UID
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uint8_t Opcode;
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/// The form field from the record
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uint8_t Form;
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/// The segment override field from the record
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uint8_t SegOvr;
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/// The hasOpSizePrefix field from the record
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bool HasOpSizePrefix;
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/// The hasAdSizePrefix field from the record
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bool HasAdSizePrefix;
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/// The hasREX_WPrefix field from the record
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bool HasREX_WPrefix;
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/// The hasVEXPrefix field from the record
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bool HasVEXPrefix;
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/// The hasVEX_4VPrefix field from the record
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bool HasVEX_4VPrefix;
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/// The hasVEX_4VOp3Prefix field from the record
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bool HasVEX_4VOp3Prefix;
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/// The hasVEX_WPrefix field from the record
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bool HasVEX_WPrefix;
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/// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
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bool HasVEX_LPrefix;
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/// The hasMemOp4Prefix field from the record
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bool HasMemOp4Prefix;
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/// The ignoreVEX_L field from the record
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bool IgnoresVEX_L;
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/// The hasLockPrefix field from the record
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bool HasLockPrefix;
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/// The isCodeGenOnly filed from the record
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bool IsCodeGenOnly;
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// Whether the instruction has the predicate "In64BitMode"
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bool Is64Bit;
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// Whether the instruction has the predicate "In32BitMode"
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bool Is32Bit;
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/// The instruction name as listed in the tables
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std::string Name;
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/// The AT&T AsmString for the instruction
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std::string AsmString;
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/// Indicates whether the instruction is SSE
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bool IsSSE;
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/// Indicates whether the instruction has FR operands - MOVs with FR operands
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/// are typically ignored
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bool HasFROperands;
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/// Indicates whether the instruction should be emitted into the decode
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/// tables; regardless, it will be emitted into the instruction info table
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bool ShouldBeEmitted;
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/// The operands of the instruction, as listed in the CodeGenInstruction.
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/// They are not one-to-one with operands listed in the MCInst; for example,
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/// memory operands expand to 5 operands in the MCInst
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const std::vector<CGIOperandList::OperandInfo>* Operands;
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/// The description of the instruction that is emitted into the instruction
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/// info table
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InstructionSpecifier* Spec;
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/// insnContext - Returns the primary context in which the instruction is
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/// valid.
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///
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/// @return - The context in which the instruction is valid.
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InstructionContext insnContext() const;
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enum filter_ret {
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FILTER_STRONG, // instruction has no place in the instruction tables
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FILTER_WEAK, // instruction may conflict, and should be eliminated if
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// it does
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FILTER_NORMAL // instruction should have high priority and generate an
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// error if it conflcits with any other FILTER_NORMAL
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// instruction
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};
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/// filter - Determines whether the instruction should be decodable. Some
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/// instructions are pure intrinsics and use unencodable operands; many
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/// synthetic instructions are duplicates of other instructions; other
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/// instructions only differ in the logical way in which they are used, and
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/// have the same decoding. Because these would cause decode conflicts,
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/// they must be filtered out.
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///
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/// @return - The degree of filtering to be applied (see filter_ret).
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filter_ret filter() const;
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/// hasFROperands - Returns true if any operand is a FR operand.
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bool hasFROperands() const;
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/// typeFromString - Translates an operand type from the string provided in
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/// the LLVM tables to an OperandType for use in the operand specifier.
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///
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/// @param s - The string, as extracted by calling Rec->getName()
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/// on a CodeGenInstruction::OperandInfo.
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/// @param isSSE - Indicates whether the instruction is an SSE
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/// instruction. For SSE instructions, immediates are
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/// fixed-size rather than being affected by the
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/// mandatory OpSize prefix.
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/// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
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/// prefix. If it does, 32-bit register operands stay
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/// 32-bit regardless of the operand size.
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/// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
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/// prefix. If it does not, then 16-bit register
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/// operands stay 16-bit.
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/// @return - The operand's type.
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static OperandType typeFromString(const std::string& s,
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bool isSSE,
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bool hasREX_WPrefix,
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bool hasOpSizePrefix);
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/// immediateEncodingFromString - Translates an immediate encoding from the
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/// string provided in the LLVM tables to an OperandEncoding for use in
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/// the operand specifier.
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///
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/// @param s - See typeFromString().
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/// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
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/// prefix. If it does not, then 16-bit immediate
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/// operands stay 16-bit.
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/// @return - The operand's encoding.
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static OperandEncoding immediateEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
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/// handles operands that are in the REG field of the ModR/M byte.
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static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
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/// handles operands that are in the REG field of the ModR/M byte.
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static OperandEncoding roRegisterEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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static OperandEncoding memoryEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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static OperandEncoding relocationEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
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bool hasOpSizePrefix);
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static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
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bool HasOpSizePrefix);
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/// handleOperand - Converts a single operand from the LLVM table format to
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/// the emitted table format, handling any duplicate operands it encounters
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/// and then one non-duplicate.
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///
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/// @param optional - Determines whether to assert that the
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/// operand exists.
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/// @param operandIndex - The index into the generated operand table.
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/// Incremented by this function one or more
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/// times to reflect possible duplicate
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/// operands).
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/// @param physicalOperandIndex - The index of the current operand into the
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/// set of non-duplicate ('physical') operands.
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/// Incremented by this function once.
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/// @param numPhysicalOperands - The number of non-duplicate operands in the
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/// instructions.
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/// @param operandMapping - The operand mapping, which has an entry for
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/// each operand that indicates whether it is a
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/// duplicate, and of what.
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void handleOperand(bool optional,
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unsigned &operandIndex,
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unsigned &physicalOperandIndex,
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unsigned &numPhysicalOperands,
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const unsigned *operandMapping,
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OperandEncoding (*encodingFromString)
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(const std::string&,
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bool hasOpSizePrefix));
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/// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
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/// filters out many instructions, at various points in decoding we
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/// determine that the instruction should not actually be decodable. In
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/// particular, MMX MOV instructions aren't emitted, but they're only
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/// identified during operand parsing.
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///
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/// @return - true if at this point we believe the instruction should be
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/// emitted; false if not. This will return false if filter() returns false
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/// once emitInstructionSpecifier() has been called.
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bool shouldBeEmitted() const {
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return ShouldBeEmitted;
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}
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/// emitInstructionSpecifier - Loads the instruction specifier for the current
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/// instruction into a DisassemblerTables.
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///
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/// \param tables The DisassemblerTables to populate with the specifier for
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/// the current instruction.
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void emitInstructionSpecifier(DisassemblerTables &tables);
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/// emitDecodePath - Populates the proper fields in the decode tables
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/// corresponding to the decode paths for this instruction.
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///
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/// \param tables The DisassemblerTables to populate with the decode
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/// decode information for the current instruction.
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void emitDecodePath(DisassemblerTables &tables) const;
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/// Constructor - Initializes a RecognizableInstr with the appropriate fields
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/// from a CodeGenInstruction.
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///
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/// \param tables The DisassemblerTables that the specifier will be added to.
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/// \param insn The CodeGenInstruction to extract information from.
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/// \param uid The unique ID of the current instruction.
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RecognizableInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid);
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public:
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/// processInstr - Accepts a CodeGenInstruction and loads decode information
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/// for it into a DisassemblerTables if appropriate.
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///
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/// \param tables The DiassemblerTables to be populated with decode
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/// information.
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/// \param insn The CodeGenInstruction to be used as a source for this
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/// information.
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/// \param uid The unique ID of the instruction.
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static void processInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid);
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};
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} // namespace X86Disassembler
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} // namespace llvm
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#endif
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