39028e8396
Due to allocating tlb contexts on the fly, we only ever need to demap the primary context, non-primary contexts have already been implicitly flushed by context switching. All we really need to tell is if its a kernel demap or not, and its easier just to compare against the kernel_pmap which is a constant.
259 lines
7.0 KiB
C
259 lines
7.0 KiB
C
/*-
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* Copyright (c) 2001 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TLB_H_
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#define _MACHINE_TLB_H_
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#define TLB_SLOT_COUNT 64
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#define TLB_SLOT_TSB_KERNEL_MIN 62 /* XXX */
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#define TLB_SLOT_KERNEL 63
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#define TLB_DAR_SLOT_SHIFT (3)
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#define TLB_DAR_SLOT(slot) ((slot) << TLB_DAR_SLOT_SHIFT)
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#define TAR_VPN_SHIFT (13)
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#define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1)
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#define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK)
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#define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK)
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#define TLB_DEMAP_ID_SHIFT (4)
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#define TLB_DEMAP_ID_PRIMARY (0)
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#define TLB_DEMAP_ID_SECONDARY (1)
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#define TLB_DEMAP_ID_NUCLEUS (2)
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#define TLB_DEMAP_TYPE_SHIFT (6)
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#define TLB_DEMAP_TYPE_PAGE (0)
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#define TLB_DEMAP_TYPE_CONTEXT (1)
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#define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK)
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#define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT)
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#define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT)
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#define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
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#define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
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#define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
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#define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
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#define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
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#define TLB_CTX_KERNEL (0)
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#define TLB_CTX_USER_MIN (1)
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#define TLB_CTX_USER_MAX (8192)
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#define TLB_DTLB (1 << 0)
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#define TLB_ITLB (1 << 1)
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#define MMU_SFSR_ASI_SHIFT (16)
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#define MMU_SFSR_FT_SHIFT (7)
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#define MMU_SFSR_E_SHIFT (6)
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#define MMU_SFSR_CT_SHIFT (4)
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#define MMU_SFSR_PR_SHIFT (3)
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#define MMU_SFSR_W_SHIFT (2)
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#define MMU_SFSR_OW_SHIFT (1)
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#define MMU_SFSR_FV_SHIFT (0)
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#define MMU_SFSR_ASI_SIZE (8)
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#define MMU_SFSR_FT_SIZE (6)
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#define MMU_SFSR_CT_SIZE (2)
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#define MMU_SFSR_W (1L << MMU_SFSR_W_SHIFT)
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extern int kernel_tlb_slots;
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extern struct tte *kernel_ttes;
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/*
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* Some tlb operations must be atomical, so no interrupt or trap can be allowed
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* while they are in progress. Traps should not happen, but interrupts need to
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* be explicitely disabled. critical_enter() cannot be used here, since it only
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* disables soft interrupts.
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* XXX: is something like this needed elsewhere, too?
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*/
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static __inline void
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tlb_dtlb_context_primary_demap(void)
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{
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stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_DMMU_DEMAP, 0);
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membar(Sync);
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}
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static __inline void
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tlb_dtlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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u_int ctx;
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ctx = pm->pm_context[PCPU_GET(cpuid)];
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if (ctx == TLB_CTX_KERNEL) {
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stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
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ASI_DMMU_DEMAP, 0);
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membar(Sync);
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} else if (ctx != -1) {
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stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
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ASI_DMMU_DEMAP, 0);
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membar(Sync);
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}
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}
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static __inline void
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tlb_dtlb_store(vm_offset_t va, u_long ctx, struct tte tte)
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{
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u_long pst;
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pst = intr_disable();
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stxa(AA_DMMU_TAR, ASI_DMMU,
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TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
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stxa(0, ASI_DTLB_DATA_IN_REG, tte.tte_data);
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membar(Sync);
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intr_restore(pst);
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}
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static __inline void
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tlb_dtlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
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{
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u_long pst;
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pst = intr_disable();
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stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
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stxa(TLB_DAR_SLOT(slot), ASI_DTLB_DATA_ACCESS_REG, tte.tte_data);
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membar(Sync);
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intr_restore(pst);
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}
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static __inline void
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tlb_itlb_context_primary_demap(void)
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{
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stxa(TLB_DEMAP_PRIMARY | TLB_DEMAP_CONTEXT, ASI_IMMU_DEMAP, 0);
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membar(Sync);
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}
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static __inline void
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tlb_itlb_page_demap(struct pmap *pm, vm_offset_t va)
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{
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u_int ctx;
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ctx = pm->pm_context[PCPU_GET(cpuid)];
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if (ctx == TLB_CTX_KERNEL) {
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stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_NUCLEUS | TLB_DEMAP_PAGE,
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ASI_IMMU_DEMAP, 0);
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flush(KERNBASE);
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} else if (ctx != -1) {
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stxa(TLB_DEMAP_VA(va) | TLB_DEMAP_PRIMARY | TLB_DEMAP_PAGE,
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ASI_IMMU_DEMAP, 0);
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membar(Sync);
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}
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}
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static __inline void
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tlb_itlb_store(vm_offset_t va, u_long ctx, struct tte tte)
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{
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u_long pst;
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pst = intr_disable();
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stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
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stxa(0, ASI_ITLB_DATA_IN_REG, tte.tte_data);
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if (ctx == TLB_CTX_KERNEL)
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flush(va);
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else {
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/*
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* flush probably not needed and impossible here, no access to
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* user page.
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*/
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membar(Sync);
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}
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intr_restore(pst);
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}
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static __inline void
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tlb_context_demap(struct pmap *pm)
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{
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u_int ctx;
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ctx = pm->pm_context[PCPU_GET(cpuid)];
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if (ctx != -1) {
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tlb_dtlb_context_primary_demap();
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tlb_itlb_context_primary_demap();
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}
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}
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static __inline void
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tlb_itlb_store_slot(vm_offset_t va, u_long ctx, struct tte tte, int slot)
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{
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u_long pst;
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pst = intr_disable();
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stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(va) | TLB_TAR_CTX(ctx));
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stxa(TLB_DAR_SLOT(slot), ASI_ITLB_DATA_ACCESS_REG, tte.tte_data);
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flush(va);
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intr_restore(pst);
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}
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static __inline void
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tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va)
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{
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if (tlb & TLB_DTLB)
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tlb_dtlb_page_demap(pm, va);
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if (tlb & TLB_ITLB)
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tlb_itlb_page_demap(pm, va);
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}
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static __inline void
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tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
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{
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for (; start < end; start += PAGE_SIZE)
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tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, start);
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}
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static __inline void
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tlb_tte_demap(struct tte tte, struct pmap *pm)
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{
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tlb_page_demap(TD_GET_TLB(tte.tte_data), pm, TV_GET_VA(tte.tte_vpn));
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}
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static __inline void
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tlb_store(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte)
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{
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KASSERT(ctx != -1, ("tlb_store: invalid context"));
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if (tlb & TLB_DTLB)
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tlb_dtlb_store(va, ctx, tte);
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if (tlb & TLB_ITLB)
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tlb_itlb_store(va, ctx, tte);
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}
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static __inline void
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tlb_store_slot(u_int tlb, vm_offset_t va, u_long ctx, struct tte tte, int slot)
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{
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KASSERT(ctx != -1, ("tlb_store_slot: invalid context"));
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if (tlb & TLB_DTLB)
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tlb_dtlb_store_slot(va, ctx, tte, slot);
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if (tlb & TLB_ITLB)
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tlb_itlb_store_slot(va, ctx, tte, slot);
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}
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#endif /* !_MACHINE_TLB_H_ */
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