6ce70ec7f9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
100 lines
4.9 KiB
C
100 lines
4.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2004 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from: OpenBSD: clkbrdreg.h,v 1.2 2004/10/01 15:36:30 jason Exp
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_FHC_CLKBRDREG_H_
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#define _SPARC64_FHC_CLKBRDREG_H_
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/* register bank 0 */
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#define CLK_CF_REG2 0x20 /* clock frequency register 2 */
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#define CLK_CF_REG2_REN_RCONS 0x80 /* reset enable: remote console */
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#define CLK_CF_REG2_REN_GEN 0x40 /* reset enable: frequency change */
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#define CLK_CF_REG2_REN_WDOG 0x20 /* reset enable: watchdog */
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#define CLK_CF_REG2_DIV1 0x10 /* CPU module divisor bit 1 */
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#define CLK_CF_REG2_RANGE 0x0c /* clock range */
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#define CLK_CF_REG2_DIV0 0x02 /* CPU module divisor bit 0 */
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#define CLK_CF_REG2_FREQ8 0x01 /* frequency bit 8 */
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/* register bank 1 */
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#define CLK_CTRL 0x00 /* system control register */
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#define CLK_CTRL_IEN_FAN 0x80 /* intr enable: fan failure */
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#define CLK_CTRL_IEN_DC 0x40 /* intr enable: power supply DC */
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#define CLK_CTRL_IEN_AC 0x20 /* intr enable: AC power */
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#define CLK_CTRL_IEN_BRD 0x10 /* intr enable: board insert */
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#define CLK_CTRL_POFF 0x08 /* turn off system power */
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#define CLK_CTRL_LLED 0x04 /* left led (reversed) */
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#define CLK_CTRL_MLED 0x02 /* middle led */
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#define CLK_CTRL_RLED 0x01 /* right led */
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#define CLK_STS1 0x10 /* system status register 1 */
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#define CLK_STS1_SLOTS_MASK 0xc0 /* system status 1 slots mask */
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#define CLK_STS1_SLOTS_16 0x40 /* 16 slots */
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#define CLK_STS1_SLOTS_8 0xc0 /* 8 slots */
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#define CLK_STS1_SLOTS_4 0x80 /* 4 slots */
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#define CLK_STS1_SLOTS_TESTBED 0x00 /* test machine */
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#define CLK_STS1_SECURE 0x20 /* key in position secure (reversed) */
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#define CLK_STS1_FAN 0x10 /* fan tray present (reversed) */
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#define CLK_STS1_BRD 0x08 /* board inserted (reversed) */
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#define CLK_STS1_PS0 0x04 /* power supply 0 present (reversed) */
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#define CLK_STS1_RST_WDOG 0x02 /* rst by: watchdog (reversed) */
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#define CLK_STS1_RST_GEN 0x01 /* rst by: freq change (reversed) */
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#define CLK_STS2 0x20 /* system status register 2 */
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#define CLK_STS2_RST_RCONS 0x80 /* rst by: remote console (reversed) */
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#define CLK_STS2_OK_PS0 0x40 /* ok: power supply 0 */
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#define CLK_STS2_OK_33V 0x20 /* ok: 3.3V on clock board */
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#define CLK_STS2_OK_50V 0x10 /* ok: 5.0V on clock board */
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#define CLK_STS2_FAIL_AC 0x08 /* failed: AC power */
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#define CLK_STS2_FAIL_FAN 0x04 /* failed: rack fans */
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#define CLK_STS2_OK_ACFAN 0x02 /* ok: 4 AC box fans */
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#define CLK_STS2_OK_KEYFAN 0x01 /* ok: keyswitch fans */
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#define CLK_PSTS1 0x30 /* power supply 1 status register */
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#define CLK_PSTS1_PS 0x80 /* power supply 1 present (reversed) */
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#define CLK_PPRES 0x40 /* power supply presence register */
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#define CLK_PPRES_CSHARE 0x80 /* current share backplane */
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#define CLK_PPRES_OK_MASK 0x7f /* precharge and peripheral pwr mask */
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#define CLK_PPRES_OK_P_5V 0x40 /* ok: peripheral 5V */
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#define CLK_PPRES_OK_P_12V 0x20 /* ok: peripheral 12V */
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#define CLK_PPRES_OK_AUX_5V 0x10 /* ok: auxiliary 5V */
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#define CLK_PPRES_OK_PP_5V 0x08 /* ok: peripheral 5V precharge */
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#define CLK_PPRES_OK_PP_12V 0x04 /* ok: peripheral 12V precharge */
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#define CLK_PPRES_OK_SP_3V 0x02 /* ok: system 3.3V precharge */
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#define CLK_PPRES_OK_SP_5V 0x01 /* ok: system 5V precharge */
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#define CLK_TEMP 0x50 /* temperature register */
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#define CLK_IDIAG 0x60 /* interrupt diagnostic register */
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#define CLK_PSTS2 0x70 /* power supply 2 status register */
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/* register bank 2 */
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#define CLKVER_SLOTS 0x00 /* clock version slots register */
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#define CLKVER_SLOTS_MASK 0x80 /* clock version slots mask */
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#define CLKVER_SLOTS_PLUS 0x00 /* plus system (reversed) */
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#endif /* !_SPARC64_FHC_CLKBRDREG_H_ */
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