b8aa843c63
- Split core DRM routines back into their own module, rather than using the nasty templated system like before. - Development-class R300 support in radeon driver (requires userland pieces, of course). - Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others. - i915 driver files, which just need to get drm_drv.c fixed to allow attachment to the drmsub device. Covers i830 through i915 integrated graphics. - savage driver files, which should require minimal changes to work. Covers the Savage3D, Savage IX/MX, Savage 4, ProSavage. - Support for color and texture tiling and HyperZ features of Radeon. Thanks to: scottl (much p4 handholding) Jung-uk Kim (helpful prodding) PR: [1] kern/76879, [2] kern/72548 Submitted by: [1] Alex, lesha at intercaf dot ru [2] Shaun Jurrens, shaun at shamz dot net
240 lines
7.0 KiB
C
240 lines
7.0 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*
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* $FreeBSD$
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*/
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/**************************************************************************
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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**************************************************************************/
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
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#define DRIVER_NAME "i915"
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#define DRIVER_DESC "Intel Graphics"
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#define DRIVER_DATE "20041217"
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/* Interface history:
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*
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* 1.1: Original.
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* 1.2: Add Power Management
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 2
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#define DRIVER_PATCHLEVEL 0
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typedef struct _drm_i915_ring_buffer {
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int tail_mask;
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unsigned long Start;
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unsigned long End;
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unsigned long Size;
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u8 *virtual_start;
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int head;
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int tail;
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int space;
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drm_local_map_t map;
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} drm_i915_ring_buffer_t;
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struct mem_block {
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struct mem_block *next;
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struct mem_block *prev;
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int start;
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int size;
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DRMFILE filp; /* 0: free, -1: heap, other: real files */
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};
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typedef struct drm_i915_private {
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drm_local_map_t *sarea;
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drm_local_map_t *mmio_map;
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drm_i915_sarea_t *sarea_priv;
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drm_i915_ring_buffer_t ring;
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void *hw_status_page;
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unsigned long counter;
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dma_addr_t dma_status_page;
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int back_offset;
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int front_offset;
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int current_page;
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int page_flipping;
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int use_mi_batchbuffer_start;
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wait_queue_head_t irq_queue;
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atomic_t irq_received;
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atomic_t irq_emitted;
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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struct mem_block *agp_heap;
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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} drm_i915_private_t;
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/* i915_dma.c */
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extern void i915_kernel_lost_context(drm_device_t * dev);
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extern void i915_driver_pretakedown(drm_device_t * dev);
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extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
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/* i915_irq.c */
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extern int i915_irq_emit(DRM_IOCTL_ARGS);
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extern int i915_irq_wait(DRM_IOCTL_ARGS);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(drm_device_t * dev);
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extern void i915_driver_irq_postinstall(drm_device_t * dev);
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extern void i915_driver_irq_uninstall(drm_device_t * dev);
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/* i915_mem.c */
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extern int i915_mem_alloc(DRM_IOCTL_ARGS);
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extern int i915_mem_free(DRM_IOCTL_ARGS);
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extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
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extern void i915_mem_takedown(struct mem_block **heap);
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extern void i915_mem_release(drm_device_t * dev,
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DRMFILE filp, struct mem_block *heap);
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#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
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#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
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#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
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#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
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#define I915_VERBOSE 0
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#define RING_LOCALS unsigned int outring, ringmask, outcount; \
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volatile char *virt;
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#define BEGIN_LP_RING(n) do { \
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if (I915_VERBOSE) \
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DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
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n, __FUNCTION__); \
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if (dev_priv->ring.space < n*4) \
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i915_wait_ring(dev, n*4, __FUNCTION__); \
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outcount = 0; \
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outring = dev_priv->ring.tail; \
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ringmask = dev_priv->ring.tail_mask; \
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virt = dev_priv->ring.virtual_start; \
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} while (0)
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#define OUT_RING(n) do { \
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if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
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*(volatile unsigned int *)(virt + outring) = n; \
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outcount++; \
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outring += 4; \
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outring &= ringmask; \
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} while (0)
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#define ADVANCE_LP_RING() do { \
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if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
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dev_priv->ring.tail = outring; \
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dev_priv->ring.space -= outcount * 4; \
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I915_WRITE(LP_RING + RING_TAIL, outring); \
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} while(0)
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extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
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#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
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#define CMD_REPORT_HEAD (7<<23)
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#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
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#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
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#define INST_PARSER_CLIENT 0x00000000
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#define INST_OP_FLUSH 0x02000000
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#define INST_FLUSH_MAP_CACHE 0x00000001
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#define BB1_START_ADDR_MASK (~0x7)
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#define BB1_PROTECTED (1<<0)
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#define BB1_UNPROTECTED (0<<0)
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#define BB2_END_ADDR_MASK (~0x7)
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#define I915REG_HWSTAM 0x02098
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#define I915REG_INT_IDENTITY_R 0x020a4
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#define I915REG_INT_MASK_R 0x020a8
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#define I915REG_INT_ENABLE_R 0x020a0
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#define SRX_INDEX 0x3c4
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#define SRX_DATA 0x3c5
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#define SR01 1
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#define SR01_SCREEN_OFF (1<<5)
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#define PPCR 0x61204
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#define PPCR_ON (1<<0)
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#define DVOB 0x61140
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#define DVOB_ON (1<<31)
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#define DVOC 0x61160
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#define DVOC_ON (1<<31)
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#define LVDS 0x61180
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#define LVDS_ON (1<<31)
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#define ADPA 0x61100
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#define ADPA_DPMS_MASK (~(3<<10))
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#define ADPA_DPMS_ON (0<<10)
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#define ADPA_DPMS_SUSPEND (1<<10)
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#define ADPA_DPMS_STANDBY (2<<10)
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#define ADPA_DPMS_OFF (3<<10)
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#define NOPID 0x2094
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#define LP_RING 0x2030
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#define HP_RING 0x2040
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#define RING_TAIL 0x00
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#define TAIL_ADDR 0x001FFFF8
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#define RING_HEAD 0x04
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#define HEAD_WRAP_COUNT 0xFFE00000
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#define HEAD_WRAP_ONE 0x00200000
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#define HEAD_ADDR 0x001FFFFC
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#define RING_START 0x08
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#define START_ADDR 0x0xFFFFF000
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#define RING_LEN 0x0C
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#define RING_NR_PAGES 0x001FF000
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#define RING_REPORT_MASK 0x00000006
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#define RING_REPORT_64K 0x00000002
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#define RING_REPORT_128K 0x00000004
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#define RING_NO_REPORT 0x00000000
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#define RING_VALID_MASK 0x00000001
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#define RING_VALID 0x00000001
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#define RING_INVALID 0x00000000
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#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
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#define SC_UPDATE_SCISSOR (0x1<<1)
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#define SC_ENABLE_MASK (0x1<<0)
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#define SC_ENABLE (0x1<<0)
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#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
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#define SCI_YMIN_MASK (0xffff<<16)
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#define SCI_XMIN_MASK (0xffff<<0)
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#define SCI_YMAX_MASK (0xffff<<16)
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#define SCI_XMAX_MASK (0xffff<<0)
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#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
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#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
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#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
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#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
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#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
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#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
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#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
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#define MI_BATCH_BUFFER ((0x30<<23)|1)
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#define MI_BATCH_BUFFER_START (0x31<<23)
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#define MI_BATCH_BUFFER_END (0xA<<23)
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#define MI_BATCH_NON_SECURE (1)
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#define MI_WAIT_FOR_EVENT ((0x3<<23))
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#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
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#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
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#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
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#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
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#define ASYNC_FLIP (1<<22)
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#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
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#endif
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