173 lines
3.9 KiB
Plaintext
173 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "amlogic,g12a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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periphs: periphs@ff634000 {
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compatible = "simple-bus";
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reg = <0x0 0xff634000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
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};
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hiubus: bus@ff63c000 {
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compatible = "simple-bus";
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reg = <0x0 0xff63c000 0x0 0x1c00>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
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};
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aobus: bus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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<0x0 0xffc02000 0 0x2000>,
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<0x0 0xffc04000 0 0x2000>,
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<0x0 0xffc06000 0 0x2000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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};
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apb: apb@ffe00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffe00000 0x0 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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};
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