c3f6b2cf9f
- Most of the boards are using U-Boot, u-boot embed a DTB that isn't compiled with -@ (overlay ready) so we cannot use overlays. We want overlays, overlays are nice. - The DTS life is going to linux, then sometimes it's imported in U-Boot but it depend on the SoC family, U-Boot doesn't batch import every DTS like we do. So sometimes to U-Boot DTS are very old. Or when an interesting patch in commited upstream it is in Linux X+2 (roughly 4 months from now), we then have to wait for U-Boot to catch up, that give us between 4 and 6 months to have an update. - Some boards like the Marvell ones have 3 DTS, the one in the vendor U-Boot made by Marvell themselves, the one in u-boot mainline and the one in Linux. I found that the DTS in the Marvell U-Boot have some problem with FreeBSD (especially the macchiatobin that declare node with the same address but not the same size, that is not something that the rman code can handle, it could be modified, I don't know the code well enough). Also some compatible are used when they shouldn't, for example they declare the gpio being orion-gpio while this binding requires interrupts supports, which the node doesn't have. - The above situation is mostly the same with RockChip SoCs (possibly others, those are the only SoCs I work on that have this problem). Note that importing the DTS doesn't mean that every board will use them, I don't intend to copy the DTB to the GENERIC memstick image for the Overdrive 1000/3000 for example, the ones provided by the firmware works fine. RPI3 will still stay an exception as we use the DTB provided by the rpi-firmware package, so they come from the rpi foundation linux fork.
504 lines
13 KiB
Plaintext
504 lines
13 KiB
Plaintext
/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ8074";
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compatible = "qcom,ipq8074";
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soc: soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq8074-pinctrl";
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reg = <0x1000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupt-controller;
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#interrupt-cells = <0x2>;
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serial_4_pins: serial4-pinmux {
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pins = "gpio23", "gpio24";
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function = "blsp4_uart1";
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drive-strength = <8>;
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bias-disable;
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};
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i2c_0_pins: i2c-0-pinmux {
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pins = "gpio42", "gpio43";
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function = "blsp1_i2c";
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drive-strength = <8>;
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bias-disable;
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};
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spi_0_pins: spi-0-pins {
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pins = "gpio38", "gpio39", "gpio40", "gpio41";
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function = "blsp0_spi";
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drive-strength = <8>;
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bias-disable;
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};
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hsuart_pins: hsuart-pins {
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pins = "gpio46", "gpio47", "gpio48", "gpio49";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-disable;
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};
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qpic_pins: qpic-pins {
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pins = "gpio1", "gpio3", "gpio4",
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"gpio5", "gpio6", "gpio7",
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"gpio8", "gpio10", "gpio11",
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"gpio12", "gpio13", "gpio14",
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"gpio15", "gpio16", "gpio17";
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function = "qpic";
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drive-strength = <8>;
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bias-disable;
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};
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb121000 0x1000>,
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<0xb122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb128000 0x1000>;
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status = "disabled";
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};
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};
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq8074";
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reg = <0x1800000 0x80000>;
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#clock-cells = <0x1>;
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#reset-cells = <0x1>;
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};
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blsp1_uart5: serial@78b3000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b3000 0x200>;
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interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-0 = <&serial_4_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7884000 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b1000 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 4>,
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<&blsp_dma 5>;
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dma-names = "tx", "rx";
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pinctrl-0 = <&hsuart_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 12>, <&blsp_dma 13>;
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dma-names = "tx", "rx";
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp1_i2c2: i2c@78b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 15>, <&blsp_dma 14>;
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dma-names = "rx", "tx";
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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blsp1_i2c3: i2c@78b7000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <100000>;
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dmas = <&blsp_dma 17>, <&blsp_dma 16>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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qpic_bam: dma@7984000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x7984000 0x1a000>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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qpic_nand: nand@79b0000 {
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compatible = "qcom,ipq8074-nand";
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reg = <0x79b0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcc GCC_QPIC_CLK>,
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<&gcc GCC_QPIC_AHB_CLK>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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pinctrl-0 = <&qpic_pins>;
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pinctrl-names = "default";
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status = "disabled";
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};
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pcie_phy0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x86000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy0_pipe_clk";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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pcie0: pci@20000000 {
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compatible = "qcom,pcie-ipq8074";
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reg = <0x20000000 0xf1d
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0x20000f20 0xa8
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0x80000 0x2000
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0x20100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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phys = <&pcie_phy0>;
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x20200000 0x20200000
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0 0x100000 /* downstream I/O */
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0x82000000 0 0x20300000 0x20300000
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0 0xd00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 75
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IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 78
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IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 79
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IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 83
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IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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<&gcc GCC_PCIE0_AXI_S_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>,
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<&gcc GCC_PCIE0_AUX_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux";
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resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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<&gcc GCC_PCIE0_SLEEP_ARES>,
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<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE0_AHB_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky";
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status = "disabled";
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};
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pcie_phy1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x8e000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy1_pipe_clk";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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pcie1: pci@10000000 {
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compatible = "qcom,pcie-ipq8074";
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reg = <0x10000000 0xf1d
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0x10000f20 0xa8
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0x88000 0x2000
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0x10100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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phys = <&pcie_phy1>;
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x10200000 0x10200000
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0 0x100000 /* downstream I/O */
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0x82000000 0 0x10300000 0x10300000
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0 0xd00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142
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IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 143
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IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 144
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IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 145
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IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
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<&gcc GCC_PCIE1_AXI_M_CLK>,
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<&gcc GCC_PCIE1_AXI_S_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>,
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<&gcc GCC_PCIE1_AUX_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux";
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resets = <&gcc GCC_PCIE1_PIPE_ARES>,
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<&gcc GCC_PCIE1_SLEEP_ARES>,
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<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE1_AHB_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky";
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
CPU1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
enable-method = "psci";
|
|
reg = <0x1>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
enable-method = "psci";
|
|
reg = <0x2>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
CPU3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53", "arm,armv8";
|
|
enable-method = "psci";
|
|
reg = <0x3>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
L2_0: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <0x2>;
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
clocks {
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
xo: xo {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <19200000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
};
|