freebsd-dev/sys/mips/atheros/ar71xx_chip.h
Adrian Chadd da88453012 MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
  + arge0 supports all four (two for non-Gige interfaces.)
  + arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
  + Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
  creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
  adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
  accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
  that is on the AP96 board.  Autonegotiate is working fine, but there
  still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00

37 lines
1.6 KiB
C

/*-
* Copyright (c) 2010 Adrian Chadd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
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* 1. Redistributions of source code must retain the above copyright
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* documentation and/or other materials provided with the distribution.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef __AR71XX_CHIP_H__
#define __AR71XX_CHIP_H__
extern struct ar71xx_cpu_def ar71xx_chip_def;
extern void ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed);
extern void ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_if);
#endif