This file uses VM_MEMATTR_DEVICE_NP, which it gets through header pollution somewhere with FDT enabled. Pull in vm/vm.h to make it explicit.
933 lines
25 KiB
C
933 lines
25 KiB
C
/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <vm/vm.h>
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#endif
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pci_host_generic.h>
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#include <dev/pci/pcib_private.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/smp.h>
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#include <machine/intr.h>
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#include <arm64/cavium/thunder_pcie_common.h>
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#include <arm64/cavium/thunder_pcie_pem.h>
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#include "pcib_if.h"
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#define THUNDER_PEM_DEVICE_ID 0xa020
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#define THUNDER_PEM_VENDOR_ID 0x177d
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/* ThunderX specific defines */
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#define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24))
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#define PCIERC_CFG002 0x08
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#define PCIERC_CFG006 0x18
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#define PCIERC_CFG032 0x80
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#define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)
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#define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)
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#define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF)
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#define PEM_CFG_RD 0x30
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#define PEM_CFG_LINK_MASK 0x3
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#define PEM_CFG_LINK_RDY 0x3
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#define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4)
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#define SBNUM_OFFSET 0x8
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#define SBNUM_MASK 0xFF
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#define PEM_ON_REG 0x420
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#define PEM_CTL_STATUS 0x0
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#define PEM_LINK_ENABLE (1 << 4)
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#define PEM_LINK_DLLA (1 << 29)
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#define PEM_LINK_LT (1 << 27)
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#define PEM_BUS_SHIFT (24)
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#define PEM_SLOT_SHIFT (19)
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#define PEM_FUNC_SHIFT (16)
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#define SLIX_S2M_REGX_ACC 0x874001000000UL
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#define SLIX_S2M_REGX_ACC_SIZE 0x1000
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#define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL
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#define SLI_BASE 0x880000000000UL
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#define SLI_WINDOW_SPACING 0x004000000000UL
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#define SLI_PCI_OFFSET 0x001000000000UL
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#define SLI_NODE_SHIFT (44)
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#define SLI_NODE_MASK (3)
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#define SLI_GROUP_SHIFT (40)
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#define SLI_ID_SHIFT (24)
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#define SLI_ID_MASK (7)
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#define SLI_PEMS_PER_GROUP (3)
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#define SLI_GROUPS_PER_NODE (2)
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#define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE)
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#define SLI_ACC_REG_CNT (256)
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/*
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* Each PEM device creates its own bus with
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* own address translation, so we can adjust bus addresses
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* as we want. To support 32-bit cards let's assume
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* PCI window assignment looks as following:
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*
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* 0x00000000 - 0x000FFFFF IO
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* 0x00100000 - 0xFFFFFFFF Memory
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*/
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#define PCI_IO_BASE 0x00000000UL
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#define PCI_IO_SIZE 0x00100000UL
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#define PCI_MEMORY_BASE PCI_IO_SIZE
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#define PCI_MEMORY_SIZE 0xFFF00000UL
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#define RID_PEM_SPACE 1
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static int thunder_pem_activate_resource(device_t, device_t, int, int,
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struct resource *);
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static int thunder_pem_adjust_resource(device_t, device_t, int,
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struct resource *, rman_res_t, rman_res_t);
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static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
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int *, rman_res_t, rman_res_t, rman_res_t, u_int);
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static int thunder_pem_alloc_msi(device_t, device_t, int, int, int *);
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static int thunder_pem_release_msi(device_t, device_t, int, int *);
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static int thunder_pem_alloc_msix(device_t, device_t, int *);
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static int thunder_pem_release_msix(device_t, device_t, int);
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static int thunder_pem_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
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static int thunder_pem_get_id(device_t, device_t, enum pci_id_type,
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uintptr_t *);
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static int thunder_pem_attach(device_t);
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static int thunder_pem_deactivate_resource(device_t, device_t, int, int,
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struct resource *);
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static bus_dma_tag_t thunder_pem_get_dma_tag(device_t, device_t);
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static int thunder_pem_detach(device_t);
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static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
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static int thunder_pem_link_init(struct thunder_pem_softc *);
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static int thunder_pem_maxslots(device_t);
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static int thunder_pem_probe(device_t);
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static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int,
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int);
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static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *);
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static void thunder_pem_release_all(device_t);
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static int thunder_pem_release_resource(device_t, device_t, int, int,
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struct resource *);
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static struct rman * thunder_pem_rman(struct thunder_pem_softc *, int);
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static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *,
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int, int);
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static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t);
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/* Global handlers for SLI interface */
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static bus_space_handle_t sli0_s2m_regx_base = 0;
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static bus_space_handle_t sli1_s2m_regx_base = 0;
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static device_method_t thunder_pem_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, thunder_pem_probe),
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DEVMETHOD(device_attach, thunder_pem_attach),
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DEVMETHOD(device_detach, thunder_pem_detach),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar),
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DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar),
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DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource),
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DEVMETHOD(bus_release_resource, thunder_pem_release_resource),
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DEVMETHOD(bus_adjust_resource, thunder_pem_adjust_resource),
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DEVMETHOD(bus_activate_resource, thunder_pem_activate_resource),
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DEVMETHOD(bus_deactivate_resource, thunder_pem_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_get_dma_tag, thunder_pem_get_dma_tag),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, thunder_pem_maxslots),
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DEVMETHOD(pcib_read_config, thunder_pem_read_config),
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DEVMETHOD(pcib_write_config, thunder_pem_write_config),
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DEVMETHOD(pcib_alloc_msix, thunder_pem_alloc_msix),
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DEVMETHOD(pcib_release_msix, thunder_pem_release_msix),
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DEVMETHOD(pcib_alloc_msi, thunder_pem_alloc_msi),
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DEVMETHOD(pcib_release_msi, thunder_pem_release_msi),
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DEVMETHOD(pcib_map_msi, thunder_pem_map_msi),
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DEVMETHOD(pcib_get_id, thunder_pem_get_id),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(pcib, thunder_pem_driver, thunder_pem_methods,
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sizeof(struct thunder_pem_softc));
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extern struct bus_space memmap_bus;
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DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, 0, 0);
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MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);
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static int
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thunder_pem_maxslots(device_t dev)
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{
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#if 0
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/* max slots per bus acc. to standard */
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return (PCI_SLOTMAX);
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#else
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/*
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* ARM64TODO Workaround - otherwise an em(4) interface appears to be
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* present on every PCI function on the bus to which it is connected
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*/
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return (0);
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#endif
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}
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static int
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thunder_pem_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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{
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struct thunder_pem_softc *sc;
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int secondary_bus = 0;
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006);
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*result = PCIERC_CFG006_SEC_BUS(secondary_bus);
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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*result = sc->id;
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return (0);
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}
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return (ENOENT);
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}
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static int
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thunder_pem_write_ivar(device_t dev, device_t child, int index,
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uintptr_t value)
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{
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return (ENOENT);
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}
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static int
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thunder_pem_activate_resource(device_t dev, device_t child, int type, int rid,
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struct resource *r)
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{
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int err;
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bus_addr_t paddr;
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bus_size_t psize;
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bus_space_handle_t vaddr;
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struct thunder_pem_softc *sc;
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if ((err = rman_activate_resource(r)) != 0)
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return (err);
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sc = device_get_softc(dev);
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/*
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* If this is a memory resource, map it into the kernel.
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*/
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if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
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paddr = (bus_addr_t)rman_get_start(r);
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psize = (bus_size_t)rman_get_size(r);
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paddr = range_addr_pci_to_phys(sc->ranges, paddr);
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err = bus_space_map(&memmap_bus, paddr, psize, 0, &vaddr);
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if (err != 0) {
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rman_deactivate_resource(r);
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return (err);
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}
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rman_set_bustag(r, &memmap_bus);
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rman_set_virtual(r, (void *)vaddr);
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rman_set_bushandle(r, vaddr);
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}
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return (0);
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}
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/*
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* This function is an exact copy of nexus_deactivate_resource()
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* Keep it up-to-date with all changes in nexus. To be removed
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* once bus-mapping interface is developed.
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*/
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static int
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thunder_pem_deactivate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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bus_size_t psize;
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bus_space_handle_t vaddr;
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psize = (bus_size_t)rman_get_size(r);
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vaddr = rman_get_bushandle(r);
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if (vaddr != 0) {
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bus_space_unmap(&memmap_bus, vaddr, psize);
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rman_set_virtual(r, NULL);
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rman_set_bushandle(r, 0);
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}
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return (rman_deactivate_resource(r));
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}
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static int
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thunder_pem_adjust_resource(device_t dev, device_t child, int type,
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struct resource *res, rman_res_t start, rman_res_t end)
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{
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struct thunder_pem_softc *sc;
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struct rman *rm;
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sc = device_get_softc(dev);
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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if (type == PCI_RES_BUS)
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return (pci_domain_adjust_bus(sc->id, child, res, start, end));
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#endif
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rm = thunder_pem_rman(sc, type);
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if (rm == NULL)
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return (bus_generic_adjust_resource(dev, child, type, res,
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start, end));
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if (!rman_is_region_manager(res, rm))
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/*
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* This means a child device has a memory or I/O
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* resource not from you which shouldn't happen.
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*/
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return (EINVAL);
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return (rman_adjust_resource(res, start, end));
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}
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static bus_dma_tag_t
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thunder_pem_get_dma_tag(device_t dev, device_t child)
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{
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struct thunder_pem_softc *sc;
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sc = device_get_softc(dev);
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return (sc->dmat);
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}
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static int
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thunder_pem_alloc_msi(device_t pci, device_t child, int count, int maxcount,
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int *irqs)
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{
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device_t bus;
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bus = device_get_parent(pci);
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return (PCIB_ALLOC_MSI(device_get_parent(bus), child, count, maxcount,
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irqs));
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}
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static int
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thunder_pem_release_msi(device_t pci, device_t child, int count, int *irqs)
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{
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device_t bus;
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bus = device_get_parent(pci);
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return (PCIB_RELEASE_MSI(device_get_parent(bus), child, count, irqs));
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}
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static int
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thunder_pem_alloc_msix(device_t pci, device_t child, int *irq)
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{
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device_t bus;
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bus = device_get_parent(pci);
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return (PCIB_ALLOC_MSIX(device_get_parent(bus), child, irq));
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}
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static int
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thunder_pem_release_msix(device_t pci, device_t child, int irq)
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{
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device_t bus;
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bus = device_get_parent(pci);
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return (PCIB_RELEASE_MSIX(device_get_parent(bus), child, irq));
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}
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static int
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thunder_pem_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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{
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device_t bus;
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bus = device_get_parent(pci);
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return (PCIB_MAP_MSI(device_get_parent(bus), child, irq, addr, data));
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}
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static int
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thunder_pem_get_id(device_t pci, device_t child, enum pci_id_type type,
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uintptr_t *id)
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{
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int bsf;
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int pem;
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if (type != PCI_ID_MSI)
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return (pcib_get_id(pci, child, type, id));
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bsf = pci_get_rid(child);
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/* PEM (PCIe MAC/root complex) number is equal to domain */
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pem = pci_get_domain(child);
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/*
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* Set appropriate device ID (passed by the HW along with
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* the transaction to memory) for different root complex
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* numbers using hard-coded domain portion for each group.
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*/
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if (pem < 3)
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*id = (0x1 << PCI_RID_DOMAIN_SHIFT) | bsf;
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else if (pem < 6)
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*id = (0x3 << PCI_RID_DOMAIN_SHIFT) | bsf;
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else if (pem < 9)
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*id = (0x9 << PCI_RID_DOMAIN_SHIFT) | bsf;
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else if (pem < 12)
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*id = (0xB << PCI_RID_DOMAIN_SHIFT) | bsf;
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else
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return (ENXIO);
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return (0);
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}
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static int
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thunder_pem_identify(device_t dev)
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{
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struct thunder_pem_softc *sc;
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rman_res_t start;
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sc = device_get_softc(dev);
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start = rman_get_start(sc->reg);
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/* Calculate PEM designations from its address */
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sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK;
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sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) +
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(SLI_PEMS_PER_NODE * sc->node);
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sc->sli = sc->id % SLI_PEMS_PER_GROUP;
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sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE;
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sc->sli_window_base = SLI_BASE |
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(((uint64_t)sc->node) << SLI_NODE_SHIFT) |
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((uint64_t)sc->sli_group << SLI_GROUP_SHIFT);
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sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli;
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return (0);
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}
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static void
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thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc,
|
|
int sli_group, int slix)
|
|
{
|
|
uint64_t regval;
|
|
bus_space_handle_t handle = 0;
|
|
|
|
KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index"));
|
|
|
|
if (sli_group == 0)
|
|
handle = sli0_s2m_regx_base;
|
|
else if (sli_group == 1)
|
|
handle = sli1_s2m_regx_base;
|
|
else
|
|
device_printf(sc->dev, "SLI group is not correct\n");
|
|
|
|
if (handle) {
|
|
/* Clear lower 32-bits of the SLIx register */
|
|
regval = bus_space_read_8(sc->reg_bst, handle,
|
|
PEM_CFG_SLIX_TO_REG(slix));
|
|
regval &= ~(0xFFFFFFFFUL);
|
|
bus_space_write_8(sc->reg_bst, handle,
|
|
PEM_CFG_SLIX_TO_REG(slix), regval);
|
|
}
|
|
}
|
|
|
|
static int
|
|
thunder_pem_link_init(struct thunder_pem_softc *sc)
|
|
{
|
|
uint64_t regval;
|
|
|
|
/* check whether PEM is safe to access. */
|
|
regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG);
|
|
if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) {
|
|
device_printf(sc->dev, "PEM%d is not ON\n", sc->id);
|
|
return (ENXIO);
|
|
}
|
|
|
|
regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS);
|
|
regval |= PEM_LINK_ENABLE;
|
|
bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval);
|
|
|
|
/* Wait 1ms as per Cavium specification */
|
|
DELAY(1000);
|
|
|
|
regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032);
|
|
|
|
if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) {
|
|
device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n",
|
|
sc->id);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
thunder_pem_init(struct thunder_pem_softc *sc)
|
|
{
|
|
int i, retval = 0;
|
|
|
|
retval = thunder_pem_link_init(sc);
|
|
if (retval) {
|
|
device_printf(sc->dev, "%s failed\n", __func__);
|
|
return retval;
|
|
}
|
|
|
|
/* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */
|
|
for (i = 0; i < SLI_ACC_REG_CNT; i++) {
|
|
thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i);
|
|
}
|
|
|
|
return (retval);
|
|
}
|
|
|
|
static uint64_t
|
|
thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)
|
|
{
|
|
uint64_t data;
|
|
|
|
/* Write to ADDR register */
|
|
bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD,
|
|
PEM_CFG_RD_REG_ALIGN(reg));
|
|
bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8,
|
|
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
|
|
/* Read from DATA register */
|
|
data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh,
|
|
PEM_CFG_RD));
|
|
|
|
return (data);
|
|
}
|
|
|
|
static uint32_t
|
|
thunder_pem_read_config(device_t dev, u_int bus, u_int slot,
|
|
u_int func, u_int reg, int bytes)
|
|
{
|
|
uint64_t offset;
|
|
uint32_t data;
|
|
struct thunder_pem_softc *sc;
|
|
bus_space_tag_t t;
|
|
bus_space_handle_t h;
|
|
|
|
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
|
|
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
|
|
return (~0U);
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Calculate offset */
|
|
offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
|
|
(func << PEM_FUNC_SHIFT);
|
|
t = sc->reg_bst;
|
|
h = sc->pem_sli_base;
|
|
|
|
bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
|
|
PCIE_REGMAX, 0, &h);
|
|
|
|
switch (bytes) {
|
|
case 1:
|
|
data = bus_space_read_1(t, h, reg);
|
|
break;
|
|
case 2:
|
|
data = le16toh(bus_space_read_2(t, h, reg));
|
|
break;
|
|
case 4:
|
|
data = le32toh(bus_space_read_4(t, h, reg));
|
|
break;
|
|
default:
|
|
data = ~0U;
|
|
break;
|
|
}
|
|
|
|
bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
|
|
|
|
return (data);
|
|
}
|
|
|
|
static void
|
|
thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
|
|
u_int func, u_int reg, uint32_t val, int bytes)
|
|
{
|
|
uint64_t offset;
|
|
struct thunder_pem_softc *sc;
|
|
bus_space_tag_t t;
|
|
bus_space_handle_t h;
|
|
|
|
if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
|
|
(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
|
|
return;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Calculate offset */
|
|
offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
|
|
(func << PEM_FUNC_SHIFT);
|
|
t = sc->reg_bst;
|
|
h = sc->pem_sli_base;
|
|
|
|
bus_space_map(sc->reg_bst, sc->sli_window_base + offset,
|
|
PCIE_REGMAX, 0, &h);
|
|
|
|
switch (bytes) {
|
|
case 1:
|
|
bus_space_write_1(t, h, reg, val);
|
|
break;
|
|
case 2:
|
|
bus_space_write_2(t, h, reg, htole16(val));
|
|
break;
|
|
case 4:
|
|
bus_space_write_4(t, h, reg, htole32(val));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
bus_space_unmap(sc->reg_bst, h, PCIE_REGMAX);
|
|
}
|
|
|
|
static struct resource *
|
|
thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
|
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
|
|
{
|
|
struct thunder_pem_softc *sc = device_get_softc(dev);
|
|
struct rman *rm = NULL;
|
|
struct resource *res;
|
|
device_t parent_dev;
|
|
|
|
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
|
|
if (type == PCI_RES_BUS)
|
|
return (pci_domain_alloc_bus(sc->id, child, rid, start, end,
|
|
count, flags));
|
|
#endif
|
|
rm = thunder_pem_rman(sc, type);
|
|
if (rm == NULL) {
|
|
/* Find parent device. On ThunderX we know an exact path. */
|
|
parent_dev = device_get_parent(device_get_parent(dev));
|
|
return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start,
|
|
end, count, flags));
|
|
}
|
|
|
|
if (!RMAN_IS_DEFAULT_RANGE(start, end)) {
|
|
/*
|
|
* We might get PHYS addresses here inherited from EFI.
|
|
* Convert to PCI if necessary.
|
|
*/
|
|
if (range_addr_is_phys(sc->ranges, start, count)) {
|
|
start = range_addr_phys_to_pci(sc->ranges, start);
|
|
end = start + count - 1;
|
|
}
|
|
}
|
|
|
|
if (bootverbose) {
|
|
device_printf(dev,
|
|
"thunder_pem_alloc_resource: start=%#lx, end=%#lx, count=%#lx\n",
|
|
start, end, count);
|
|
}
|
|
|
|
res = rman_reserve_resource(rm, start, end, count, flags, child);
|
|
if (res == NULL)
|
|
goto fail;
|
|
|
|
rman_set_rid(res, *rid);
|
|
|
|
if (flags & RF_ACTIVE)
|
|
if (bus_activate_resource(child, type, *rid, res)) {
|
|
rman_release_resource(res);
|
|
goto fail;
|
|
}
|
|
|
|
return (res);
|
|
|
|
fail:
|
|
if (bootverbose) {
|
|
device_printf(dev, "%s FAIL: type=%d, rid=%d, "
|
|
"start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
|
|
__func__, type, *rid, start, end, count, flags);
|
|
}
|
|
|
|
return (NULL);
|
|
}
|
|
|
|
static int
|
|
thunder_pem_release_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
device_t parent_dev;
|
|
#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
|
|
struct thunder_pem_softc *sc = device_get_softc(dev);
|
|
|
|
if (type == PCI_RES_BUS)
|
|
return (pci_domain_release_bus(sc->id, child, rid, res));
|
|
#endif
|
|
/* Find parent device. On ThunderX we know an exact path. */
|
|
parent_dev = device_get_parent(device_get_parent(dev));
|
|
|
|
if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT))
|
|
return (BUS_RELEASE_RESOURCE(parent_dev, child,
|
|
type, rid, res));
|
|
|
|
return (rman_release_resource(res));
|
|
}
|
|
|
|
static struct rman *
|
|
thunder_pem_rman(struct thunder_pem_softc *sc, int type)
|
|
{
|
|
|
|
switch (type) {
|
|
case SYS_RES_IOPORT:
|
|
return (&sc->io_rman);
|
|
case SYS_RES_MEMORY:
|
|
return (&sc->mem_rman);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return (NULL);
|
|
}
|
|
|
|
static int
|
|
thunder_pem_probe(device_t dev)
|
|
{
|
|
uint16_t pci_vendor_id;
|
|
uint16_t pci_device_id;
|
|
|
|
pci_vendor_id = pci_get_vendor(dev);
|
|
pci_device_id = pci_get_device(dev);
|
|
|
|
if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) &&
|
|
(pci_device_id == THUNDER_PEM_DEVICE_ID)) {
|
|
device_set_desc_copy(dev, THUNDER_PEM_DESC);
|
|
return (0);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
thunder_pem_attach(device_t dev)
|
|
{
|
|
struct resource_map_request req;
|
|
struct resource_map map;
|
|
devclass_t pci_class;
|
|
device_t parent;
|
|
struct thunder_pem_softc *sc;
|
|
int error;
|
|
int rid;
|
|
int tuple;
|
|
uint64_t base, size;
|
|
struct rman *rman;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
/* Allocate memory for resource */
|
|
pci_class = devclass_find("pci");
|
|
parent = device_get_parent(dev);
|
|
if (device_get_devclass(parent) == pci_class)
|
|
rid = PCIR_BAR(0);
|
|
else
|
|
rid = RID_PEM_SPACE;
|
|
|
|
sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&rid, RF_ACTIVE | RF_UNMAPPED);
|
|
if (sc->reg == NULL) {
|
|
device_printf(dev, "Failed to allocate resource\n");
|
|
return (ENXIO);
|
|
}
|
|
resource_init_map_request(&req);
|
|
req.memattr = VM_MEMATTR_DEVICE_NP;
|
|
error = bus_map_resource(dev, SYS_RES_MEMORY, sc->reg, &req, &map);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not map memory.\n");
|
|
return (error);
|
|
}
|
|
rman_set_mapping(sc->reg, &map);
|
|
|
|
sc->reg_bst = rman_get_bustag(sc->reg);
|
|
sc->reg_bsh = rman_get_bushandle(sc->reg);
|
|
|
|
/* Create the parent DMA tag to pass down the coherent flag */
|
|
error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
|
|
1, 0, /* alignment, bounds */
|
|
BUS_SPACE_MAXADDR, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg */
|
|
BUS_SPACE_MAXSIZE, /* maxsize */
|
|
BUS_SPACE_UNRESTRICTED, /* nsegments */
|
|
BUS_SPACE_MAXSIZE, /* maxsegsize */
|
|
BUS_DMA_COHERENT, /* flags */
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
&sc->dmat);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
/* Map SLI, do it only once */
|
|
if (!sli0_s2m_regx_base) {
|
|
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
|
|
SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
|
|
}
|
|
if (!sli1_s2m_regx_base) {
|
|
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
|
|
SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
|
|
&sli1_s2m_regx_base);
|
|
}
|
|
|
|
if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
|
|
device_printf(dev,
|
|
"bus_space_map failed to map slix_s2m_regx_base\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Identify PEM */
|
|
if (thunder_pem_identify(dev) != 0)
|
|
goto fail;
|
|
|
|
/* Initialize rman and allocate regions */
|
|
sc->mem_rman.rm_type = RMAN_ARRAY;
|
|
sc->mem_rman.rm_descr = "PEM PCIe Memory";
|
|
error = rman_init(&sc->mem_rman);
|
|
if (error != 0) {
|
|
device_printf(dev, "memory rman_init() failed. error = %d\n",
|
|
error);
|
|
goto fail;
|
|
}
|
|
sc->io_rman.rm_type = RMAN_ARRAY;
|
|
sc->io_rman.rm_descr = "PEM PCIe IO";
|
|
error = rman_init(&sc->io_rman);
|
|
if (error != 0) {
|
|
device_printf(dev, "IO rman_init() failed. error = %d\n",
|
|
error);
|
|
goto fail_mem;
|
|
}
|
|
|
|
/*
|
|
* We ignore the values that may have been provided in FDT
|
|
* and configure ranges according to the below formula
|
|
* for all types of devices. This is because some DTBs provided
|
|
* by EFI do not have proper ranges property or don't have them
|
|
* at all.
|
|
*/
|
|
/* Fill memory window */
|
|
sc->ranges[0].pci_base = PCI_MEMORY_BASE;
|
|
sc->ranges[0].size = PCI_MEMORY_SIZE;
|
|
sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
|
|
sc->ranges[0].pci_base;
|
|
sc->ranges[0].flags = SYS_RES_MEMORY;
|
|
|
|
/* Fill IO window */
|
|
sc->ranges[1].pci_base = PCI_IO_BASE;
|
|
sc->ranges[1].size = PCI_IO_SIZE;
|
|
sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
|
|
sc->ranges[1].pci_base;
|
|
sc->ranges[1].flags = SYS_RES_IOPORT;
|
|
|
|
for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
|
|
base = sc->ranges[tuple].pci_base;
|
|
size = sc->ranges[tuple].size;
|
|
if (size == 0)
|
|
continue; /* empty range element */
|
|
|
|
rman = thunder_pem_rman(sc, sc->ranges[tuple].flags);
|
|
if (rman != NULL)
|
|
error = rman_manage_region(rman, base,
|
|
base + size - 1);
|
|
else
|
|
error = EINVAL;
|
|
if (error) {
|
|
device_printf(dev,
|
|
"rman_manage_region() failed. error = %d\n", error);
|
|
rman_fini(&sc->mem_rman);
|
|
return (error);
|
|
}
|
|
if (bootverbose) {
|
|
device_printf(dev,
|
|
"\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n",
|
|
sc->ranges[tuple].pci_base,
|
|
sc->ranges[tuple].phys_base,
|
|
sc->ranges[tuple].size,
|
|
sc->ranges[tuple].flags);
|
|
}
|
|
}
|
|
|
|
if (thunder_pem_init(sc)) {
|
|
device_printf(dev, "Failure during PEM init\n");
|
|
goto fail_io;
|
|
}
|
|
|
|
device_add_child(dev, "pci", -1);
|
|
|
|
return (bus_generic_attach(dev));
|
|
|
|
fail_io:
|
|
rman_fini(&sc->io_rman);
|
|
fail_mem:
|
|
rman_fini(&sc->mem_rman);
|
|
fail:
|
|
bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
|
|
return (ENXIO);
|
|
}
|
|
|
|
static void
|
|
thunder_pem_release_all(device_t dev)
|
|
{
|
|
struct thunder_pem_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
rman_fini(&sc->io_rman);
|
|
rman_fini(&sc->mem_rman);
|
|
|
|
if (sc->reg != NULL)
|
|
bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
|
|
}
|
|
|
|
static int
|
|
thunder_pem_detach(device_t dev)
|
|
{
|
|
|
|
thunder_pem_release_all(dev);
|
|
|
|
return (0);
|
|
}
|