c38fe8789a
We have it in the includes path and this will help the transition to the new device-tree import in sys/contrib
232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <dt-bindings/clock/tegra210-car.h>
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#include "tegra210_car.h"
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struct super_mux_def {
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struct clknode_init_def clkdef;
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uint32_t base_reg;
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uint32_t flags;
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};
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#define PLIST(x) static const char *x[]
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#define SM(_id, cn, pl, r) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cn, \
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.clkdef.parent_names = pl, \
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.clkdef.parent_cnt = nitems(pl), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.base_reg = r, \
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}
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PLIST(cclk_g_parents) = {
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"clk_m", NULL, "clk_s", NULL,
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"pllP_out0", "pllP_out4", NULL, NULL,
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"pllX_out0", "dfllCPU_out_alias", NULL, NULL,
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NULL, NULL, "pllX_out0_alias", "dfllCPU_out",
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};
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PLIST(cclk_lp_parents) = {
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"clk_m", NULL, "clk_s", NULL,
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"pllP_out0", "pllP_out4", NULL, NULL,
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"pllX_out0", "dfllCPU_out_alias", NULL, NULL,
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NULL, NULL, "pllX_out0_alias", "dfllCPU_out",
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};
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PLIST(sclk_parents) = {
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"clk_m", "pllC_out1", "pllC4_out3", "pllP_out0",
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"pllP_out2", "pllC4_out1", "clk_s", "pllC4_out1",
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};
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static struct super_mux_def super_mux_def[] = {
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SM(TEGRA210_CLK_CCLK_G, "cclk_g", cclk_g_parents, CCLKG_BURST_POLICY),
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SM(TEGRA210_CLK_CCLK_LP, "cclk_lp", cclk_lp_parents, CCLKLP_BURST_POLICY),
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SM(TEGRA210_CLK_SCLK, "sclk", sclk_parents, SCLK_BURST_POLICY),
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};
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static int super_mux_init(struct clknode *clk, device_t dev);
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static int super_mux_set_mux(struct clknode *clk, int idx);
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struct super_mux_sc {
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device_t clkdev;
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uint32_t base_reg;
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uint32_t flags;
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int mux;
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};
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static clknode_method_t super_mux_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, super_mux_init),
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CLKNODEMETHOD(clknode_set_mux, super_mux_set_mux),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(tegra210_super_mux, tegra210_super_mux_class, super_mux_methods,
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sizeof(struct super_mux_sc), clknode_class);
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/* Mux status. */
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#define SUPER_MUX_STATE_STDBY 0
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#define SUPER_MUX_STATE_IDLE 1
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#define SUPER_MUX_STATE_RUN 2
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#define SUPER_MUX_STATE_IRQ 3
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#define SUPER_MUX_STATE_FIQ 4
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/* Mux register bits. */
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#define SUPER_MUX_STATE_BIT_SHIFT 28
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#define SUPER_MUX_STATE_BIT_MASK 0xF
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/* State is Priority encoded */
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#define SUPER_MUX_STATE_BIT_STDBY 0x00
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#define SUPER_MUX_STATE_BIT_IDLE 0x01
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#define SUPER_MUX_STATE_BIT_RUN 0x02
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#define SUPER_MUX_STATE_BIT_IRQ 0x04
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#define SUPER_MUX_STATE_BIT_FIQ 0x08
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#define SUPER_MUX_MUX_WIDTH 4
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static uint32_t
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super_mux_get_state(uint32_t reg)
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{
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reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK;
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if (reg & SUPER_MUX_STATE_BIT_FIQ)
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return (SUPER_MUX_STATE_FIQ);
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if (reg & SUPER_MUX_STATE_BIT_IRQ)
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return (SUPER_MUX_STATE_IRQ);
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if (reg & SUPER_MUX_STATE_BIT_RUN)
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return (SUPER_MUX_STATE_RUN);
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if (reg & SUPER_MUX_STATE_BIT_IDLE)
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return (SUPER_MUX_STATE_IDLE);
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return (SUPER_MUX_STATE_STDBY);
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}
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static int
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super_mux_init(struct clknode *clk, device_t dev)
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{
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struct super_mux_sc *sc;
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uint32_t reg;
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int shift, state;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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RD4(sc, sc->base_reg, ®);
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DEVICE_UNLOCK(sc);
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state = super_mux_get_state(reg);
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if ((state != SUPER_MUX_STATE_RUN) &&
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(state != SUPER_MUX_STATE_IDLE)) {
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panic("Unexpected super mux state: %u", state);
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}
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shift = state * SUPER_MUX_MUX_WIDTH;
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sc->mux = (reg >> shift) & ((1 << SUPER_MUX_MUX_WIDTH) - 1);
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clknode_init_parent_idx(clk, sc->mux);
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return(0);
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}
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static int
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super_mux_set_mux(struct clknode *clk, int idx)
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{
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struct super_mux_sc *sc;
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int shift, state;
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uint32_t reg, dummy;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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RD4(sc, sc->base_reg, ®);
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state = super_mux_get_state(reg);
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if ((state != SUPER_MUX_STATE_RUN) &&
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(state != SUPER_MUX_STATE_IDLE)) {
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panic("Unexpected super mux state: %u", state);
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}
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shift = (state - 1) * SUPER_MUX_MUX_WIDTH;
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sc->mux = idx;
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reg &= ~(((1 << SUPER_MUX_MUX_WIDTH) - 1) << shift);
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reg |= idx << shift;
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WR4(sc, sc->base_reg, reg);
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RD4(sc, sc->base_reg, &dummy);
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DEVICE_UNLOCK(sc);
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return(0);
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}
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static int
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super_mux_register(struct clkdom *clkdom, struct super_mux_def *clkdef)
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{
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struct clknode *clk;
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struct super_mux_sc *sc;
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clk = clknode_create(clkdom, &tegra210_super_mux_class,
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&clkdef->clkdef);
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if (clk == NULL)
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return (1);
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sc = clknode_get_softc(clk);
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sc->clkdev = clknode_get_device(clk);
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sc->base_reg = clkdef->base_reg;
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sc->flags = clkdef->flags;
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clknode_register(clkdom, clk);
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return (0);
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}
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void
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tegra210_super_mux_clock(struct tegra210_car_softc *sc)
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{
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int i, rv;
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for (i = 0; i < nitems(super_mux_def); i++) {
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rv = super_mux_register(sc->clkdom, &super_mux_def[i]);
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if (rv != 0)
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panic("super_mux_register failed");
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}
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}
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