398 lines
11 KiB
C
398 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/intr.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofwpci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_dw.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/pmap.h>
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#include "pcib_if.h"
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/* APB Registers */
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#define PCIE_CLIENT_GENERAL_CON 0x0000
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#define DEVICE_TYPE_MASK 0x00f0
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#define DEVICE_TYPE_RC (1<<6)
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#define LINK_REQ_RST_GRT (1<<3)
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#define LTSSM_ENABLE (1<<2)
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#define PCIE_CLIENT_INTR_MASK_MSG_RX 0x0018
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#define PCIE_CLIENT_INTR_MASK_LEGACY 0x001c
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#define PCIE_CLIENT_INTR_MASK_ERR 0x0020
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#define PCIE_CLIENT_INTR_MASK_MISC 0x0024
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#define PCIE_CLIENT_INTR_MASK_PMC 0x0028
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#define PCIE_CLIENT_GENERAL_DEBUG_INFO 0x0104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x0180
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#define APP_LSSTM_ENABLE_ENHANCE (1<<4)
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#define PCIE_CLIENT_LTSSM_STATUS 0x0300
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#define RDLH_LINK_UP (1<<17)
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#define SMLH_LINK_UP (1<<16)
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#define SMLH_LTSSM_STATE_MASK 0x003f
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#define SMLH_LTSSM_STATE_LINK_UP ((1<<4) | (1<<0))
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struct rk3568_pcie_softc {
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struct pci_dw_softc dw_sc; /* Must be first */
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device_t dev;
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int apb_rid;
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struct resource *apb_res;
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int dbi_rid;
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struct resource *dbi_res;
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int irq_rid;
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struct resource *irq_res;
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void *irq_handle;
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phandle_t node;
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struct gpiobus_pin *reset_gpio;
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clk_t aclk_mst, aclk_slv, aclk_dbi, pclk, aux;
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regulator_t regulator;
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hwreset_t hwreset;
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phy_t phy;
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};
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,rk3568-pcie", 1},
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{NULL, 0}
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};
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static void
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rk3568_intr(void *data)
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{
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struct rk3568_pcie_softc *sc = data;
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device_printf(sc->dev, "INTERRUPT!!\n");
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}
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static int
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rk3568_pcie_get_link(device_t dev, bool *status)
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{
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struct rk3568_pcie_softc *sc = device_get_softc(dev);
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uint32_t val;
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val = bus_read_4(sc->apb_res, PCIE_CLIENT_LTSSM_STATUS);
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if (((val & (RDLH_LINK_UP | SMLH_LINK_UP)) ==
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(RDLH_LINK_UP | SMLH_LINK_UP)) &&
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((val & SMLH_LTSSM_STATE_MASK) == SMLH_LTSSM_STATE_LINK_UP))
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*status = true;
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else
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*status = false;
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return (0);
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}
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static int
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rk3568_pcie_init_soc(device_t dev)
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{
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struct rk3568_pcie_softc *sc = device_get_softc(dev);
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int err, count;
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bool status;
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/* Assert reset */
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if (hwreset_assert(sc->hwreset))
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device_printf(dev, "Could not assert reset\n");
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/* Powerup PCIe */
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if (regulator_enable(sc->regulator))
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device_printf(dev, "Cannot enable regulator\n");
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/* Enable PHY */
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if (phy_enable(sc->phy))
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device_printf(dev, "Cannot enable phy\n");
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/* Deassert reset */
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if (hwreset_deassert(sc->hwreset))
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device_printf(dev, "Could not deassert reset\n");
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/* Enable clocks */
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if ((err = clk_enable(sc->aclk_mst))) {
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device_printf(dev, "Could not enable aclk_mst clk\n");
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return (ENXIO);
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}
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if ((err = clk_enable(sc->aclk_slv))) {
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device_printf(dev, "Could not enable aclk_slv clk\n");
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return (ENXIO);
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}
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if ((err = clk_enable(sc->aclk_dbi))) {
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device_printf(dev, "Could not enable aclk_dbi clk\n");
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return (ENXIO);
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}
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if ((err = clk_enable(sc->pclk))) {
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device_printf(dev, "Could not enable pclk clk\n");
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return (ENXIO);
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}
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if ((err = clk_enable(sc->aux))) {
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device_printf(dev, "Could not enable aux clk\n");
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return (ENXIO);
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}
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/* Set Root Complex (RC) mode */
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bus_write_4(sc->apb_res, PCIE_CLIENT_HOT_RESET_CTRL,
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(APP_LSSTM_ENABLE_ENHANCE << 16) | APP_LSSTM_ENABLE_ENHANCE);
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bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON,
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(DEVICE_TYPE_MASK << 16) | DEVICE_TYPE_RC);
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/* Assert reset PCIe */
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if ((err = gpio_pin_set_active(sc->reset_gpio, false)))
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device_printf(dev, "reset_gpio set failed\n");
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/* Start Link Training and Status State Machine (LTSSM) */
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bus_write_4(sc->apb_res, PCIE_CLIENT_GENERAL_CON,
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(LINK_REQ_RST_GRT | LTSSM_ENABLE) << 16 |
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(LINK_REQ_RST_GRT | LTSSM_ENABLE));
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DELAY(100000);
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/* Release reset */
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if ((err = gpio_pin_set_active(sc->reset_gpio, true)))
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device_printf(dev, "reset_gpio release failed\n");
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/* Wait for link up/stable */
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for (count = 20; count; count--) {
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rk3568_pcie_get_link(dev, &status);
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if (status)
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break;
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DELAY(100000);
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if (count == 0) {
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device_printf(dev, "Link up timeout!\n");
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return (ENXIO);
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}
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}
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if ((err = pci_dw_init(dev)))
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return (ENXIO);
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/* Delay to have things settle */
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DELAY(100000);
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/* Enable all MSG interrupts */
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bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_MSG_RX, 0x7fff0000);
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/* Enable all Legacy interrupts */
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bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_LEGACY, 0x00ff0000);
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/* Enable all Error interrupts */
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bus_write_4(sc->apb_res, PCIE_CLIENT_INTR_MASK_ERR, 0x0fff0000);
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return (0);
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}
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static int
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rk3568_pcie_detach(device_t dev)
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{
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struct rk3568_pcie_softc *sc = device_get_softc(dev);
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/* Release allocated resources */
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if (sc->irq_handle)
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bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
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if (sc->phy)
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phy_release(sc->phy);
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if (sc->aux)
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clk_release(sc->aux);
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if (sc->pclk)
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clk_release(sc->pclk);
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if (sc->aclk_dbi)
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clk_release(sc->aclk_dbi);
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if (sc->aclk_slv)
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clk_release(sc->aclk_slv);
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if (sc->aclk_mst)
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clk_release(sc->aclk_mst);
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if (sc->hwreset)
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hwreset_release(sc->hwreset);
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if (sc->regulator)
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regulator_release(sc->regulator);
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if (sc->irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
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sc->irq_res);
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if (sc->dbi_res)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->dbi_rid,
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sc->dbi_res);
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if (sc->apb_res)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->apb_rid,
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sc->apb_res);
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return (0);
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}
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static int
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rk3568_pcie_attach(device_t dev)
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{
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struct rk3568_pcie_softc *sc = device_get_softc(dev);
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int error;
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sc->dev = dev;
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sc->node = ofw_bus_get_node(dev);
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/* Setup resources */
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if ((error = ofw_bus_find_string_index(sc->node, "reg-names", "apb",
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&sc->apb_rid))) {
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device_printf(dev, "Cannot get APB memory: %d\n", error);
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goto fail;
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}
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if (!(sc->apb_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->apb_rid, RF_ACTIVE))) {
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device_printf(dev, "Cannot allocate APB resource\n");
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goto fail;
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}
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if ((error = ofw_bus_find_string_index(sc->node, "reg-names", "dbi",
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&sc->dbi_rid))) {
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device_printf(dev, "Cannot get DBI memory: %d\n", error);
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goto fail;
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}
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if (!(sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->dbi_rid, RF_ACTIVE))) {
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device_printf(dev, "Cannot allocate DBI resource\n");
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goto fail;
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}
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if (!(sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&sc->irq_rid, RF_ACTIVE | RF_SHAREABLE))) {
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device_printf(dev, "Cannot allocate IRQ resource\n");
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goto fail;
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}
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/* Get regulator if present */
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if (regulator_get_by_ofw_property(dev, 0, "vpcie3v3-supply",
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&sc->regulator)) {
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device_printf(dev, "Cannot get regulator\n");
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goto fail;
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}
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/* Get reset */
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if (hwreset_get_by_ofw_name(dev, 0, "pipe", &sc->hwreset)) {
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device_printf(dev, "Can not get reset\n");
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goto fail;
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}
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/* Get GPIO reset */
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if (OF_hasprop(sc->node, "reset-gpios")) {
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if (gpio_pin_get_by_ofw_property(dev, sc->node, "reset-gpios",
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&sc->reset_gpio)) {
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device_printf(dev, "Cannot get reset-gpios\n");
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goto fail;
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}
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gpio_pin_setflags(sc->reset_gpio, GPIO_PIN_OUTPUT);
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gpio_pin_set_active(sc->reset_gpio, true);
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}
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/* Get clocks */
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if (clk_get_by_ofw_name(dev, 0, "aclk_mst", &sc->aclk_mst)) {
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device_printf(dev, "Can not get aclk_mst clk\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "aclk_slv", &sc->aclk_slv)) {
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device_printf(dev, "Can not get aclk_slv clk\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "aclk_dbi", &sc->aclk_dbi)) {
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device_printf(dev, "Can not get aclk_dbi clk\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) {
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device_printf(dev, "Can not get pclk clk\n");
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goto fail;
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}
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if (clk_get_by_ofw_name(dev, 0, "aux", &sc->aux)) {
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device_printf(dev, "Can not get aux clk\n");
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goto fail;
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}
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/* Get PHY */
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if (phy_get_by_ofw_name(dev, 0, "pcie-phy", &sc->phy)) {
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device_printf(dev, "Cannot get 'pcie-phy'\n");
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goto fail;
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}
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if ((error = rk3568_pcie_init_soc(dev)))
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goto fail;
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/* Enable interrupt */
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if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, rk3568_intr, sc, &sc->irq_handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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goto fail;
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}
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return (bus_generic_attach(dev));
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fail:
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rk3568_pcie_detach(dev);
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return (ENXIO);
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}
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static int
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rk3568_pcie_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "RockChip RK3568 PCI-express controller");
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return (BUS_PROBE_DEFAULT);
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}
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static device_method_t rk3568_pcie_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, rk3568_pcie_probe),
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DEVMETHOD(device_attach, rk3568_pcie_attach),
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DEVMETHOD(device_detach, rk3568_pcie_detach),
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/* PCI DW interface */
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DEVMETHOD(pci_dw_get_link, rk3568_pcie_get_link),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, rk3568_pcie_driver, rk3568_pcie_methods,
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sizeof(struct rk3568_pcie_softc), pci_dw_driver);
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DRIVER_MODULE(rk3568_pcie, simplebus, rk3568_pcie_driver, NULL, NULL);
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