39f92a76a9
In many cases this avoids an extra lookup, since the callers always have pm at hand. We can also eliminate several assertions, mostly for pm != NULL. The class methods are an internal interface, and the callers already handle such a scenario. No functional change intended. Reviewed by: jkoshy MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D39915
534 lines
12 KiB
C
534 lines
12 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/pmc_mdep.h>
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#include <machine/cpu.h>
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static int armv7_npmcs;
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struct armv7_event_code_map {
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enum pmc_event pe_ev;
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uint8_t pe_code;
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};
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#define PMC_EV_CPU_CYCLES 0xFF
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/*
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* Per-processor information.
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*/
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struct armv7_cpu {
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struct pmc_hw *pc_armv7pmcs;
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};
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static struct armv7_cpu **armv7_pcpu;
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/*
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* Interrupt Enable Set Register
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*/
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static __inline void
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armv7_interrupt_enable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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cp15_pminten_set(reg);
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}
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/*
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* Interrupt Clear Set Register
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*/
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static __inline void
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armv7_interrupt_disable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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cp15_pminten_clr(reg);
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}
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/*
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* Counter Set Enable Register
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*/
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static __inline void
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armv7_counter_enable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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cp15_pmcnten_set(reg);
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}
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/*
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* Counter Clear Enable Register
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*/
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static __inline void
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armv7_counter_disable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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cp15_pmcnten_clr(reg);
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}
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/*
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* Performance Count Register N
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*/
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static uint32_t
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armv7_pmcn_read(unsigned int pmc, uint32_t evsel)
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{
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if (evsel == PMC_EV_CPU_CYCLES) {
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return ((uint32_t)cp15_pmccntr_get());
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}
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KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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cp15_pmselr_set(pmc);
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return (cp15_pmxevcntr_get());
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}
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static uint32_t
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armv7_pmcn_write(unsigned int pmc, uint32_t reg)
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{
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KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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cp15_pmselr_set(pmc);
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cp15_pmxevcntr_set(reg);
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return (reg);
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}
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static int
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armv7_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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enum pmc_event pe;
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uint32_t config;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row index %d", __LINE__, ri));
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if (a->pm_class != PMC_CLASS_ARMV7)
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return (EINVAL);
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pe = a->pm_ev;
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config = (pe & EVENT_ID_MASK);
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pm->pm_md.pm_armv7.pm_armv7_evsel = config;
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PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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}
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static int
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armv7_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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{
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pmc_value_t tmp;
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register_t s;
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u_int reg;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row index %d", __LINE__, ri));
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s = intr_disable();
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tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel);
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/* Check if counter has overflowed */
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
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reg = (1u << 31);
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else
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reg = (1u << ri);
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if ((cp15_pmovsr_get() & reg) != 0) {
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/* Clear Overflow Flag */
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cp15_pmovsr_set(reg);
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pm->pm_pcpu_state[cpu].pps_overflowcnt++;
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/* Reread counter in case we raced. */
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tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel);
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}
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tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt;
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intr_restore(s);
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PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
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/*
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* Clamp value to 0 if the counter just overflowed,
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* otherwise the returned reload count would wrap to a
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* huge value.
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*/
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if ((tmp & (1ull << 63)) == 0)
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tmp = 0;
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else
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tmp = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
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}
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*v = tmp;
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return 0;
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}
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static int
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armv7_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
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{
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32;
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
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cp15_pmccntr_set(v);
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else
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armv7_pmcn_write(ri, v);
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return 0;
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}
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static int
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armv7_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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}
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static int
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armv7_start_pmc(int cpu, int ri, struct pmc *pm)
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{
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uint32_t config;
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config = pm->pm_md.pm_armv7.pm_armv7_evsel;
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/*
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* Configure the event selection.
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*/
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if (config != PMC_EV_CPU_CYCLES) {
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cp15_pmselr_set(ri);
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cp15_pmxevtyper_set(config);
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} else
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ri = 31;
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/*
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* Enable the PMC.
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*/
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armv7_interrupt_enable(ri);
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armv7_counter_enable(ri);
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return 0;
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}
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static int
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armv7_stop_pmc(int cpu, int ri, struct pmc *pm)
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{
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uint32_t config;
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config = pm->pm_md.pm_armv7.pm_armv7_evsel;
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if (config == PMC_EV_CPU_CYCLES)
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ri = 31;
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/*
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* Disable the PMCs.
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*/
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armv7_counter_disable(ri);
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armv7_interrupt_disable(ri);
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return 0;
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}
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static int
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armv7_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw __diagused;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] illegal row-index %d", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return 0;
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}
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static int
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armv7_intr(struct trapframe *tf)
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{
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int retval, ri;
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struct pmc *pm;
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int error;
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int reg, cpu;
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cpu = curcpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] CPU %d out of range", __LINE__, cpu));
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retval = 0;
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for (ri = 0; ri < armv7_npmcs; ri++) {
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pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
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if (pm == NULL)
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continue;
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/* Check if counter has overflowed */
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if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES)
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reg = (1u << 31);
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else
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reg = (1u << ri);
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if ((cp15_pmovsr_get() & reg) == 0) {
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continue;
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}
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/* Clear Overflow Flag */
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cp15_pmovsr_set(reg);
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retval = 1; /* Found an interrupting PMC. */
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pm->pm_pcpu_state[cpu].pps_overflowcnt += 1;
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if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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continue;
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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error = pmc_process_interrupt(PMC_HR, pm, tf);
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if (error)
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armv7_stop_pmc(cpu, ri, pm);
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/* Reload sampling count */
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armv7_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount);
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}
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return (retval);
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}
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static int
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armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < armv7_npmcs,
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("[armv7,%d] row-index %d out of range", __LINE__, ri));
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phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri];
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snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV7-%d", ri);
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pi->pm_class = PMC_CLASS_ARMV7;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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armv7_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc;
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return 0;
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}
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static int
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armv7_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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struct armv7_cpu *pac;
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struct pmc_hw *phw;
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struct pmc_cpu *pc;
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uint32_t pmnc;
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int first_ri;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[armv7,%d] wrong cpu number %d", __LINE__, cpu));
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PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu);
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armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC,
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M_WAITOK|M_ZERO);
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pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs,
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M_PMC, M_WAITOK|M_ZERO);
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pc = pmc_pcpu[cpu];
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first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri;
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KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__));
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for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) {
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phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
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PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
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phw->phw_pmc = NULL;
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pc->pc_hwpmcs[i + first_ri] = phw;
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}
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pmnc = 0xffffffff;
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cp15_pmcnten_clr(pmnc);
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cp15_pminten_clr(pmnc);
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cp15_pmovsr_set(pmnc);
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/* Enable unit */
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pmnc = cp15_pmcr_get();
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pmnc |= ARMV7_PMNC_ENABLE;
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cp15_pmcr_set(pmnc);
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return 0;
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}
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static int
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armv7_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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uint32_t pmnc;
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pmnc = cp15_pmcr_get();
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pmnc &= ~ARMV7_PMNC_ENABLE;
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cp15_pmcr_set(pmnc);
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pmnc = 0xffffffff;
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cp15_pmcnten_clr(pmnc);
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cp15_pminten_clr(pmnc);
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cp15_pmovsr_set(pmnc);
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return 0;
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}
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struct pmc_mdep *
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pmc_armv7_initialize(void)
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{
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struct pmc_mdep *pmc_mdep;
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struct pmc_classdep *pcd;
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int idcode;
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int reg;
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reg = cp15_pmcr_get();
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armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \
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ARMV7_PMNC_N_MASK;
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idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT;
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PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs);
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/*
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* Allocate space for pointers to PMC HW descriptors and for
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* the MDEP structure used by MI code.
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*/
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armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(),
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M_PMC, M_WAITOK | M_ZERO);
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/* Just one class */
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pmc_mdep = pmc_mdep_alloc(1);
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switch (idcode) {
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case ARMV7_IDCODE_CORTEX_A9:
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9;
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break;
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default:
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case ARMV7_IDCODE_CORTEX_A8:
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/*
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* On A8 we implemented common events only,
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* so use it for the rest of machines.
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*/
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pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8;
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break;
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}
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pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7];
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pcd->pcd_caps = ARMV7_PMC_CAPS;
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pcd->pcd_class = PMC_CLASS_ARMV7;
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pcd->pcd_num = armv7_npmcs;
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pcd->pcd_ri = pmc_mdep->pmd_npmc;
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pcd->pcd_width = 32;
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|
|
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pcd->pcd_allocate_pmc = armv7_allocate_pmc;
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pcd->pcd_config_pmc = armv7_config_pmc;
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|
pcd->pcd_pcpu_fini = armv7_pcpu_fini;
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pcd->pcd_pcpu_init = armv7_pcpu_init;
|
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pcd->pcd_describe = armv7_describe;
|
|
pcd->pcd_get_config = armv7_get_config;
|
|
pcd->pcd_read_pmc = armv7_read_pmc;
|
|
pcd->pcd_release_pmc = armv7_release_pmc;
|
|
pcd->pcd_start_pmc = armv7_start_pmc;
|
|
pcd->pcd_stop_pmc = armv7_stop_pmc;
|
|
pcd->pcd_write_pmc = armv7_write_pmc;
|
|
|
|
pmc_mdep->pmd_intr = armv7_intr;
|
|
pmc_mdep->pmd_npmc += armv7_npmcs;
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|
|
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return (pmc_mdep);
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|
}
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|
|
|
void
|
|
pmc_armv7_finalize(struct pmc_mdep *md)
|
|
{
|
|
|
|
}
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