d90188eff5
A subsequent commit will instead use existing infrastructure to
exclude the files from hwpmc.ko for non-ACPI builds. Note that the
original commit left the files as optional in sys/conf/files.arm64.
This reverts commit 751d88119f
.
Sponsored by: DARPA
Differential Revision: https://reviews.freebsd.org/D38736
278 lines
7.6 KiB
C
278 lines
7.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Ampere Computing LLC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_hwpmc_hooks.h"
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <contrib/dev/acpica/include/acpi.h>
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#include <dev/acpica/acpivar.h>
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#include <dev/hwpmc/pmu_dmc620_reg.h>
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static char *pmu_dmc620_ids[] = {
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"ARMHD620",
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NULL
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};
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static struct resource_spec pmu_dmc620_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0 }
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};
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struct pmu_dmc620_softc {
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device_t sc_dev;
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int sc_unit;
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int sc_domain;
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struct resource *sc_res[2];
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void *sc_ih;
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uint32_t sc_clkdiv2_conters_hi[DMC620_CLKDIV2_COUNTERS_N];
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uint32_t sc_clk_conters_hi[DMC620_CLK_COUNTERS_N];
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uint32_t sc_saved_control[DMC620_COUNTERS_N];
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};
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#define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r))
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#define WR4(sc, r, v) bus_write_4((sc)->sc_res[0], (r), (v))
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#define MD4(sc, r, c, s) WR4((sc), (r), RD4((sc), (r)) & ~(c) | (s))
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#define CD2MD4(sc, u, r, c, s) MD4((sc), DMC620_CLKDIV2_REG((u), (r)), (c), (s))
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#define CMD4(sc, u, r, c, s) MD4((sc), DMC620_CLK_REG((u), (r)), (c), (s))
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static int pmu_dmc620_counter_overflow_intr(void *arg);
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uint32_t
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pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg)
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{
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struct pmu_dmc620_softc *sc;
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uint32_t val;
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sc = (struct pmu_dmc620_softc *)arg;
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KASSERT(cntr < DMC620_COUNTERS_N, ("Wrong counter unit %d", cntr));
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val = RD4(sc, DMC620_REG(cntr, reg));
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return (val);
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}
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void
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pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val)
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{
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struct pmu_dmc620_softc *sc;
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sc = (struct pmu_dmc620_softc *)arg;
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KASSERT(cntr < DMC620_COUNTERS_N, ("Wrong counter unit %d", cntr));
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WR4(sc, DMC620_REG(cntr, reg), val);
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}
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static int
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pmu_dmc620_acpi_probe(device_t dev)
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{
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int err;
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err = ACPI_ID_PROBE(device_get_parent(dev), dev, pmu_dmc620_ids, NULL);
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if (err <= 0)
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device_set_desc(dev, "ARM DMC-620 Memory Controller PMU");
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return (err);
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}
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static int
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pmu_dmc620_acpi_attach(device_t dev)
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{
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struct pmu_dmc620_softc *sc;
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int domain, i, u;
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const char *dname;
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dname = device_get_name(dev);
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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u = device_get_unit(dev);
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sc->sc_unit = u;
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/*
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* Ampere Altra support NUMA emulation, but DMC-620 PMU units have no
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* mapping. Emulate this with kenv/hints.
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* Format "hint.pmu_dmc620.3.domain=1".
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*/
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if ((resource_int_value(dname, u, "domain", &domain) == 0 ||
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bus_get_domain(dev, &domain) == 0) && domain < MAXMEMDOM) {
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sc->sc_domain = domain;
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}
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device_printf(dev, "domain=%d\n", domain);
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i = bus_alloc_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
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if (i != 0) {
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device_printf(dev, "cannot allocate resources for device (%d)\n",
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i);
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return (i);
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}
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/* Disable counter before enable interrupt. */
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for (i = 0; i < DMC620_CLKDIV2_COUNTERS_N; i++) {
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CD2MD4(sc, i, DMC620_COUNTER_CONTROL,
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DMC620_COUNTER_CONTROL_ENABLE, 0);
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}
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for (i = 0; i < DMC620_CLK_COUNTERS_N; i++) {
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CMD4(sc, i, DMC620_COUNTER_CONTROL,
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DMC620_COUNTER_CONTROL_ENABLE, 0);
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}
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/* Clear intr status. */
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WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
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WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
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if (sc->sc_res[1] != NULL && bus_setup_intr(dev, sc->sc_res[1],
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INTR_TYPE_MISC | INTR_MPSAFE, pmu_dmc620_counter_overflow_intr,
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NULL, sc, &sc->sc_ih)) {
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bus_release_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
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device_printf(dev, "cannot setup interrupt handler\n");
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return (ENXIO);
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}
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dmc620_pmc_register(u, sc, domain);
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return (0);
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}
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static int
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pmu_dmc620_acpi_detach(device_t dev)
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{
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struct pmu_dmc620_softc *sc;
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sc = device_get_softc(dev);
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dmc620_pmc_unregister(device_get_unit(dev));
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if (sc->sc_res[1] != NULL) {
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bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
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}
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bus_release_resources(dev, pmu_dmc620_res_spec, sc->sc_res);
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return (0);
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}
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static void
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pmu_dmc620_clkdiv2_overflow(struct trapframe *tf, struct pmu_dmc620_softc *sc,
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u_int i)
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{
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atomic_add_32(&sc->sc_clkdiv2_conters_hi[i], 1);
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/* Call dmc620 handler directly, because hook busy by arm64_intr. */
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dmc620_intr(tf, PMC_CLASS_DMC620_PMU_CD2, sc->sc_unit, i);
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}
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static void
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pmu_dmc620_clk_overflow(struct trapframe *tf, struct pmu_dmc620_softc *sc,
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u_int i)
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{
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atomic_add_32(&sc->sc_clk_conters_hi[i], 1);
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/* Call dmc620 handler directly, because hook busy by arm64_intr. */
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dmc620_intr(tf, PMC_CLASS_DMC620_PMU_C, sc->sc_unit, i);
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}
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static int
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pmu_dmc620_counter_overflow_intr(void *arg)
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{
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uint32_t clkdiv2_stat, clk_stat;
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struct pmu_dmc620_softc *sc;
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struct trapframe *tf;
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u_int i;
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tf = PCPU_GET(curthread)->td_intr_frame;
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sc = (struct pmu_dmc620_softc *) arg;
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clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2);
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clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK);
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if ((clkdiv2_stat == 0) && (clk_stat == 0))
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return (FILTER_STRAY);
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/* Stop and save states of all counters. */
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for (i = 0; i < DMC620_COUNTERS_N; i++) {
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sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i,
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DMC620_COUNTER_CONTROL));
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WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
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sc->sc_saved_control[i] & ~DMC620_COUNTER_CONTROL_ENABLE);
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}
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if (clkdiv2_stat != 0) {
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for (i = 0; i < DMC620_CLKDIV2_COUNTERS_N; i++) {
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if ((clkdiv2_stat & (1 << i)) == 0)
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continue;
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pmu_dmc620_clkdiv2_overflow(tf, sc, i);
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}
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WR4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2, 0);
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}
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if (clk_stat != 0) {
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for (i = 0; i < DMC620_CLK_COUNTERS_N; i++) {
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if ((clk_stat & (1 << i)) == 0)
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continue;
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pmu_dmc620_clk_overflow(tf, sc, i);
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}
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WR4(sc, DMC620_OVERFLOW_STATUS_CLK, 0);
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}
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/* Restore states of all counters. */
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for (i = 0; i < DMC620_COUNTERS_N; i++) {
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WR4(sc, DMC620_REG(i, DMC620_COUNTER_CONTROL),
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sc->sc_saved_control[i]);
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}
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return (FILTER_HANDLED);
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}
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static device_method_t pmu_dmc620_acpi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pmu_dmc620_acpi_probe),
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DEVMETHOD(device_attach, pmu_dmc620_acpi_attach),
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DEVMETHOD(device_detach, pmu_dmc620_acpi_detach),
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/* End */
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DEVMETHOD_END
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};
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static driver_t pmu_dmc620_acpi_driver = {
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"pmu_dmc620",
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pmu_dmc620_acpi_methods,
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sizeof(struct pmu_dmc620_softc),
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};
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DRIVER_MODULE(pmu_dmc620, acpi, pmu_dmc620_acpi_driver, 0, 0);
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/* Reverse dependency. hwpmc needs DMC-620 on ARM64. */
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MODULE_DEPEND(pmc, pmu_dmc620, 1, 1, 1);
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MODULE_VERSION(pmu_dmc620, 1);
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