d27ba30884
The Qualcomm Universal Peripherals Engine (QUP) is a unified SPI and I2C peripheral that ships with a variety of Qualcomm SoCs. It supports three transfer modes - single PIO, block PIO and DMA. This driver only supports the single PIO mode, which is enough to bootstrap the rest of the SPI NAND/NOR support and means I can do things like read the Wifi calibration data from NOR. It has some hardware support code for the other transfer modes as well as some support for split transfers (ie, transfers with no read or write phase), but I haven't yet implemented those. This driver is based on four sources - the linux driver, the u-boot driver, some initial work done for APQ8064 by mmel@, and the APQ8064 Technical Reference Manual which is surprisingly free and open to read. The linux and u-boot drivers approach a variety of things completely differently, from how PIO is done, the hardware support for re-ordering bytes in a transfer word and how the CS lines are used. Tested: * IPQ4018, SPI to NAND/NOR flash, PIO only
77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_SPI_REG_H__
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#define __QCOM_SPI_REG_H__
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#define SPI_CONFIG 0x0300
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#define SPI_CONFIG_HS_MODE (1U << 10)
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#define SPI_CONFIG_INPUT_FIRST (1U << 9)
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#define SPI_CONFIG_LOOPBACK (1U << 8)
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#define SPI_IO_CONTROL 0x0304
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#define SPI_IO_C_FORCE_CS (1U << 11)
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#define SPI_IO_C_CLK_IDLE_HIGH (1U << 10)
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#define SPI_IO_C_MX_CS_MODE (1U << 8)
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#define SPI_IO_C_CS_N_POLARITY_0 (1U << 4)
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#define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
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#define SPI_IO_C_CS_SELECT_MASK 0x000c
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#define SPI_IO_C_TRISTATE_CS (1U << 1)
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#define SPI_IO_C_NO_TRI_STATE (1U << 0)
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#define SPI_ERROR_FLAGS 0x0308
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#define SPI_ERROR_FLAGS_EN 0x030c
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#define SPI_ERROR_CLK_OVER_RUN (1U << 1)
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#define SPI_ERROR_CLK_UNDER_RUN (1U << 0)
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/*
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* Strictly this isn't true; some controllers have
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* less CS lines exposed via GPIO/pinmux.
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*/
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#define SPI_NUM_CHIPSELECTS 4
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/*
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* The maximum single SPI transaction done in any mode.
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* Ie, if you have a PIO/DMA transaction larger than
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* this then it must be split up into SPI_MAX_XFER
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* sub-transactions in the transfer loop.
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*/
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#define SPI_MAX_XFER (65536 - 64)
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/*
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* Any frequency at or above 26MHz is considered "high"
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* and will have some different parameters configured.
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*/
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#define SPI_HS_MIN_RATE 26000000
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#define SPI_MAX_RATE 50000000
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#endif /* __QCOM_SPI_REG_H__ */
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