4abe6533e9
The qualcomm TLMM (top level mode manager) is their gpio/pinmux hardware controller. Although the pinmux is generic enough to use for the IPQ/APQ series chips, I'm directly calling the IPQ4018 routines to expedite bring-up. Notably, I'm not yet implementing the interrupt support - it's not required at this stage of bring-up. Differential Revision: https://reviews.freebsd.org/D33554
89 lines
3.5 KiB
C
89 lines
3.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __QCOM_TLMM_IPQ4018_HW_H__
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#define __QCOM_TLMM_IPQ4018_HW_H__
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extern int qcom_tlmm_ipq4018_hw_pin_set_function(
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struct qcom_tlmm_softc *sc, int pin, int function);
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extern int qcom_tlmm_ipq4018_hw_pin_get_function(
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struct qcom_tlmm_softc *sc, int pin, int *function);
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extern int qcom_tlmm_ipq4018_hw_pin_set_oe_output(
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struct qcom_tlmm_softc *sc, int pin);
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extern int qcom_tlmm_ipq4018_hw_pin_set_oe_input(
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struct qcom_tlmm_softc *sc, int pin);
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extern int qcom_tlmm_ipq4018_hw_pin_get_oe_state(
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struct qcom_tlmm_softc *sc, int pin, bool *is_output);
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extern int qcom_tlmm_ipq4018_hw_pin_set_output_value(
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struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int value);
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extern int qcom_tlmm_ipq4018_hw_pin_get_output_value(
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struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int *val);
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extern int qcom_tlmm_ipq4018_hw_pin_get_input_value(
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struct qcom_tlmm_softc *sc,
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uint32_t pin, unsigned int *val);
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extern int qcom_tlmm_ipq4018_hw_pin_toggle_output_value(
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struct qcom_tlmm_softc *sc,
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uint32_t pin);
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extern int qcom_tlmm_ipq4018_hw_pin_set_pupd_config(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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qcom_tlmm_pin_pupd_config_t pupd);
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extern int qcom_tlmm_ipq4018_hw_pin_get_pupd_config(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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qcom_tlmm_pin_pupd_config_t *pupd);
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extern int qcom_tlmm_ipq4018_hw_pin_set_drive_strength(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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uint8_t drv);
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extern int qcom_tlmm_ipq4018_hw_pin_get_drive_strength(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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uint8_t *drv);
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extern int qcom_tlmm_ipq4018_hw_pin_set_vm(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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bool enable);
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extern int qcom_tlmm_ipq4018_hw_pin_get_vm(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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bool *enable);
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extern int qcom_tlmm_ipq4018_hw_pin_set_open_drain(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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bool enable);
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extern int qcom_tlmm_ipq4018_hw_pin_get_open_drain(
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struct qcom_tlmm_softc *sc, uint32_t pin,
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bool *enable);
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#endif /* __QCOM_TLMM_IPQ4018_HW_H__ */
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