189 lines
4.7 KiB
C
189 lines
4.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019-2020 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_IOMMU_SMMUVAR_H_
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#define _ARM64_IOMMU_SMMUVAR_H_
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#define SMMU_DEVSTR "ARM System Memory Management Unit"
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#define SMMU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define SMMU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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DECLARE_CLASS(smmu_driver);
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struct smmu_unit {
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struct iommu_unit iommu;
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LIST_HEAD(, smmu_domain) domain_list;
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LIST_ENTRY(smmu_unit) next;
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device_t dev;
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intptr_t xref;
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};
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struct smmu_domain {
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struct iommu_domain iodom;
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LIST_HEAD(, smmu_ctx) ctx_list;
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LIST_ENTRY(smmu_domain) next;
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u_int entries_cnt;
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struct smmu_cd *cd;
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struct pmap p;
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uint16_t asid;
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};
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struct smmu_ctx {
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struct iommu_ctx ioctx;
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struct smmu_domain *domain;
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LIST_ENTRY(smmu_ctx) next;
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device_t dev;
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bool bypass;
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int sid;
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uint16_t vendor;
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uint16_t device;
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};
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struct smmu_queue_local_copy {
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union {
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uint64_t val;
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struct {
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uint32_t prod;
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uint32_t cons;
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};
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};
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};
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struct smmu_cd {
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vm_paddr_t paddr;
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vm_size_t size;
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void *vaddr;
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};
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struct smmu_queue {
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struct smmu_queue_local_copy lc;
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vm_paddr_t paddr;
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void *vaddr;
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uint32_t prod_off;
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uint32_t cons_off;
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int size_log2;
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uint64_t base;
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};
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struct smmu_cmdq_entry {
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uint8_t opcode;
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union {
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struct {
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uint16_t asid;
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uint16_t vmid;
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vm_offset_t addr;
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bool leaf;
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} tlbi;
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struct {
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uint32_t sid;
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uint32_t ssid;
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bool leaf;
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} cfgi;
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struct {
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uint32_t sid;
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} prefetch;
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struct {
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uint64_t msiaddr;
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} sync;
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};
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};
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struct l1_desc {
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uint8_t span;
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size_t size;
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void *va;
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vm_paddr_t pa;
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};
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struct smmu_strtab {
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void *vaddr;
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uint64_t base;
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uint32_t base_cfg;
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uint32_t num_l1_entries;
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struct l1_desc *l1;
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};
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struct smmu_softc {
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device_t dev;
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struct resource *res[5];
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void *intr_cookie[3];
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uint32_t ias; /* Intermediate Physical Address */
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uint32_t oas; /* Physical Address */
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uint32_t asid_bits;
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uint32_t vmid_bits;
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uint32_t sid_bits;
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uint32_t ssid_bits;
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uint32_t pgsizes;
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uint32_t features;
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#define SMMU_FEATURE_2_LVL_STREAM_TABLE (1 << 0)
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#define SMMU_FEATURE_2_LVL_CD (1 << 1)
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#define SMMU_FEATURE_TT_LE (1 << 2)
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#define SMMU_FEATURE_TT_BE (1 << 3)
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#define SMMU_FEATURE_SEV (1 << 4)
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#define SMMU_FEATURE_MSI (1 << 5)
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#define SMMU_FEATURE_HYP (1 << 6)
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#define SMMU_FEATURE_ATS (1 << 7)
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#define SMMU_FEATURE_PRI (1 << 8)
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#define SMMU_FEATURE_STALL_FORCE (1 << 9)
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#define SMMU_FEATURE_STALL (1 << 10)
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#define SMMU_FEATURE_S1P (1 << 11)
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#define SMMU_FEATURE_S2P (1 << 12)
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#define SMMU_FEATURE_VAX (1 << 13)
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#define SMMU_FEATURE_COHERENCY (1 << 14)
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#define SMMU_FEATURE_RANGE_INV (1 << 15)
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struct smmu_queue cmdq;
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struct smmu_queue evtq;
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struct smmu_queue priq;
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struct smmu_strtab strtab;
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int sync;
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struct mtx sc_mtx;
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bitstr_t *asid_set;
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int asid_set_size;
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struct mtx asid_set_mutex;
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struct smmu_unit unit;
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uintptr_t xref;
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};
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MALLOC_DECLARE(M_SMMU);
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/* Device methods */
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int smmu_attach(device_t dev);
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int smmu_detach(device_t dev);
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struct smmu_ctx *smmu_ctx_lookup_by_sid(device_t dev, u_int sid);
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bool smmu_quirks_check(device_t dev, u_int sid, uint8_t event_id,
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uintptr_t input_addr);
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#endif /* _ARM64_IOMMU_SMMUVAR_H_ */
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