cfba8dec89
Each clock drivers if now fully subclassed, this have the advantage that we can control the probe order. Some clocks can have parents from other drivers, for example clocks in the sun8i_r driver uses clocks from the main clock driver. This worked before because the sun8i_r node is after the main ccu node in the dtb and driver are probed in DTB order. This cannot work with the Display Engine clocks as it is the first node in the DTB. Tested on: A83T, H5 A64 Tested on: A20 (kevans)
265 lines
7.6 KiB
C
265 lines
7.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#if defined(__aarch64__)
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#include "opt_soc.h"
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#endif
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <arm/allwinner/clkng/aw_ccung.h>
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#include <gnu/dts/include/dt-bindings/clock/sun8i-r-ccu.h>
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#include <gnu/dts/include/dt-bindings/reset/sun8i-r-ccu.h>
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/* Non-exported clocks */
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#define CLK_AHB0 1
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#define CLK_APB0 2
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static struct aw_ccung_reset ccu_sun8i_r_resets[] = {
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CCU_RESET(RST_APB0_IR, 0xb0, 1)
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CCU_RESET(RST_APB0_TIMER, 0xb0, 2)
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CCU_RESET(RST_APB0_RSB, 0xb0, 4)
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CCU_RESET(RST_APB0_UART, 0xb0, 6)
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};
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static struct aw_ccung_gate ccu_sun8i_r_gates[] = {
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CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0)
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CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x28, 1)
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CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2)
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CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3)
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CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4)
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CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6)
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CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7)
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};
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static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"};
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static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"};
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PREDIV_CLK(ar100_clk, CLK_AR100, /* id */
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"ar100", ar100_parents, /* name, parents */
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0x00, /* offset */
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16, 2, /* mux */
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4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
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8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
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16, 2, 2); /* prediv condition */
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PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */
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"ar100", a83t_ar100_parents, /* name, parents */
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0x00, /* offset */
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16, 2, /* mux */
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4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
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8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
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16, 2, 2); /* prediv condition */
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static const char *ahb0_parents[] = {"ar100"};
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FIXED_CLK(ahb0_clk,
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CLK_AHB0, /* id */
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"ahb0", /* name */
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ahb0_parents, /* parent */
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0, /* freq */
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1, /* mult */
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1, /* div */
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0); /* flags */
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static const char *apb0_parents[] = {"ahb0"};
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DIV_CLK(apb0_clk,
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CLK_APB0, /* id */
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"apb0", apb0_parents, /* name, parents */
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0x0c, /* offset */
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0, 2, /* shift, width */
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0, NULL); /* flags, div table */
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static const char *r_ccu_ir_parents[] = {"osc32k", "osc24M"};
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NM_CLK(r_ccu_ir_clk,
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CLK_IR, /* id */
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"ir", r_ccu_ir_parents, /* names, parents */
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0x54, /* offset */
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0, 4, 0, 0, /* N factor */
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16, 2, 0, 0, /* M flags */
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24, 2, /* mux */
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31, /* gate */
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AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */
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static const char *a83t_ir_parents[] = {"osc16M", "osc24M"};
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static struct aw_clk_nm_def a83t_ir_clk = {
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.clkdef = {
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.id = CLK_IR,
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.name = "ir",
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.parent_names = a83t_ir_parents,
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.parent_cnt = nitems(a83t_ir_parents),
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},
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.offset = 0x54,
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.n = {.shift = 0, .width = 4, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
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.m = {.shift = 16, .width = 2},
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.prediv = {
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.cond_shift = 24,
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.cond_width = 2,
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.cond_value = 0,
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.value = 16
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},
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.mux_shift = 24,
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.mux_width = 2,
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.flags = AW_CLK_HAS_MUX | AW_CLK_HAS_PREDIV,
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};
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static struct aw_ccung_clk clks[] = {
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{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk},
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{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
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{ .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
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{ .type = AW_CLK_NM, .clk.nm = &r_ccu_ir_clk},
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};
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static struct aw_ccung_clk a83t_clks[] = {
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{ .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &a83t_ar100_clk},
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{ .type = AW_CLK_DIV, .clk.div = &apb0_clk},
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{ .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk},
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{ .type = AW_CLK_NM, .clk.nm = &a83t_ir_clk},
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};
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static struct ofw_compat_data compat_data[] = {
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#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5)
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{ "allwinner,sun8i-h3-r-ccu", 1 },
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#endif
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#if defined(SOC_ALLWINNER_A64)
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{ "allwinner,sun50i-a64-r-ccu", 1 },
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#endif
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{ NULL, 0},
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};
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static int
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ccu_sun8i_r_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner SUN8I_R Clock Control Unit NG");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ccu_sun8i_r_attach(device_t dev)
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{
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struct aw_ccung_softc *sc;
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sc = device_get_softc(dev);
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sc->resets = ccu_sun8i_r_resets;
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sc->nresets = nitems(ccu_sun8i_r_resets);
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sc->gates = ccu_sun8i_r_gates;
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sc->ngates = nitems(ccu_sun8i_r_gates);
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sc->clks = clks;
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sc->nclks = nitems(clks);
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return (aw_ccung_attach(dev));
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}
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static device_method_t ccu_sun8i_r_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ccu_sun8i_r_probe),
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DEVMETHOD(device_attach, ccu_sun8i_r_attach),
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DEVMETHOD_END
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};
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static devclass_t ccu_sun8i_r_devclass;
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DEFINE_CLASS_1(ccu_sun8i_r, ccu_sun8i_r_driver, ccu_sun8i_r_methods,
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sizeof(struct aw_ccung_softc), aw_ccung_driver);
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EARLY_DRIVER_MODULE(ccu_sun8i_r, simplebus, ccu_sun8i_r_driver,
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ccu_sun8i_r_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST);
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static int
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ccu_a83t_r_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-r-ccu"))
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return (ENXIO);
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device_set_desc(dev, "Allwinner A83T_R Clock Control Unit NG");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ccu_a83t_r_attach(device_t dev)
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{
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struct aw_ccung_softc *sc;
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sc = device_get_softc(dev);
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sc->resets = ccu_sun8i_r_resets;
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sc->nresets = nitems(ccu_sun8i_r_resets);
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sc->gates = ccu_sun8i_r_gates;
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sc->ngates = nitems(ccu_sun8i_r_gates);
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sc->clks = a83t_clks;
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sc->nclks = nitems(a83t_clks);
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return (aw_ccung_attach(dev));
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}
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static device_method_t ccu_a83t_r_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ccu_a83t_r_probe),
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DEVMETHOD(device_attach, ccu_a83t_r_attach),
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DEVMETHOD_END
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};
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static devclass_t ccu_a83t_r_devclass;
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DEFINE_CLASS_1(ccu_a83t_r, ccu_a83t_r_driver, ccu_a83t_r_methods,
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sizeof(struct aw_ccung_softc), aw_ccung_driver);
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EARLY_DRIVER_MODULE(ccu_a83t_r, simplebus, ccu_a83t_r_driver,
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ccu_a83t_r_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST);
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