587 lines
18 KiB
C
587 lines
18 KiB
C
/*-
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* Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* $FreeBSD$
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*/
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#define CS_89x0_IO_PORTS 0x0020
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#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
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/* offset 2h -> Model/Product Number */
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/* offset 3h -> Chip Revision Number */
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#define PP_ISAIOB 0x0020 /* IO base address */
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#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
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#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
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#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
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#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
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#define PP_ISASOF 0x0026 /* ISA DMA offset */
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#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
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#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
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#define PP_CS8920_ISAMemB 0x0348 /* Memory base */
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/* EEPROM data and command registers */
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#define PP_EECMD 0x0040 /* NVR Interface Command register */
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#define PP_EEData 0x0042 /* NVR Interface Data Register */
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#define PP_DebugReg 0x0044 /* Debug Register */
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#define PP_RxCFG 0x0102 /* Rx Bus config */
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#define PP_RxCTL 0x0104 /* Receive Control Register */
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#define PP_TxCFG 0x0106 /* Transmit Config Register */
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#define PP_TxCMD 0x0108 /* Transmit Command Register */
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#define PP_BufCFG 0x010A /* Bus configuration Register */
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#define PP_LineCTL 0x0112 /* Line Config Register */
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#define PP_SelfCTL 0x0114 /* Self Command Register */
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#define PP_BusCTL 0x0116 /* ISA bus control Register */
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#define PP_TestCTL 0x0118 /* Test Register */
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#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
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#define PP_ISQ 0x0120 /* Interrupt Status */
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#define PP_RxEvent 0x0124 /* Rx Event Register */
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#define PP_TxEvent 0x0128 /* Tx Event Register */
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#define PP_BufEvent 0x012C /* Bus Event Register */
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#define PP_RxMiss 0x0130 /* Receive Miss Count */
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#define PP_TxCol 0x0132 /* Transmit Collision Count */
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#define PP_LineST 0x0134 /* Line State Register */
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#define PP_SelfST 0x0136 /* Self State register */
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#define PP_BusST 0x0138 /* Bus Status */
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#define PP_TDR 0x013C /* Time Domain Reflectometry */
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#define PP_AutoNegST 0x013E /* Auto Neg Status */
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#define PP_TxCommand 0x0144 /* Tx Command */
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#define PP_TxLength 0x0146 /* Tx Length */
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#define PP_LAF 0x0150 /* Hash Table */
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#define PP_IA 0x0158 /* Physical Address Register */
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#define PP_RxStatus 0x0400 /* Receive start of frame */
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#define PP_RxLength 0x0402 /* Receive Length of frame */
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#define PP_RxFrame 0x0404 /* Receive frame pointer */
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#define PP_TxFrame 0x0A00 /* Transmit frame pointer */
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/*
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* Primary I/O Base Address. If no I/O base is supplied by the user, then this
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* can be used as the default I/O base to access the PacketPage Area.
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*/
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#define DEFAULTIOBASE 0x0300
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#define FIRST_IO 0x020C /* First I/O port to check */
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#define LAST_IO 0x037C /* Last I/O port to check (+10h) */
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#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
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#define ADD_SIG 0x3000 /* Expected ID signature */
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#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
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#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
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/* Mask to find out the types of registers */
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#define REG_TYPE_MASK 0x001F
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/* Eeprom Commands */
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#define ERSE_WR_ENBL 0x00F0
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#define ERSE_WR_DISABLE 0x0000
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/* Defines Control/Config register quintuplet numbers */
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#define RX_BUF_CFG 0x0003
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#define RX_CONTROL 0x0005
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#define TX_CFG 0x0007
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#define TX_COMMAND 0x0009
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#define BUF_CFG 0x000B
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#define LINE_CONTROL 0x0013
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#define SELF_CONTROL 0x0015
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#define BUS_CONTROL 0x0017
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#define TEST_CONTROL 0x0019
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/* Defines Status/Count registers quintuplet numbers */
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#define RX_EVENT 0x0004
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#define TX_EVENT 0x0008
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#define BUF_EVENT 0x000C
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#define RX_MISS_COUNT 0x0010
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#define TX_COL_COUNT 0x0012
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#define LINE_STATUS 0x0014
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#define SELF_STATUS 0x0016
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#define BUS_STATUS 0x0018
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#define TDR 0x001C
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/*
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* PP_RxCFG - Receive Configuration and Interrupt Mask
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* bit definition - Read/write
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*/
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#define SKIP_1 0x0040
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#define RX_STREAM_ENBL 0x0080
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#define RX_OK_ENBL 0x0100
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#define RX_DMA_ONLY 0x0200
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#define AUTO_RX_DMA 0x0400
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#define BUFFER_CRC 0x0800
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#define RX_CRC_ERROR_ENBL 0x1000
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#define RX_RUNT_ENBL 0x2000
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#define RX_EXTRA_DATA_ENBL 0x4000
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/* PP_RxCTL - Receive Control bit definition - Read/write */
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#define RX_IA_HASH_ACCEPT 0x0040
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#define RX_PROM_ACCEPT 0x0080
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#define RX_OK_ACCEPT 0x0100
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#define RX_MULTCAST_ACCEPT 0x0200
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#define RX_IA_ACCEPT 0x0400
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#define RX_BROADCAST_ACCEPT 0x0800
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#define RX_BAD_CRC_ACCEPT 0x1000
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#define RX_RUNT_ACCEPT 0x2000
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#define RX_EXTRA_DATA_ACCEPT 0x4000
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#define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \
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RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT)
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/*
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* Default receive mode - individually addressed, broadcast, and error free
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*/
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#define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
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/*
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* PP_TxCFG - Transmit Configuration Interrupt Mask
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* bit definition - Read/write
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*/
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#define TX_LOST_CRS_ENBL 0x0040
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#define TX_SQE_ERROR_ENBL 0x0080
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#define TX_OK_ENBL 0x0100
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#define TX_LATE_COL_ENBL 0x0200
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#define TX_JBR_ENBL 0x0400
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#define TX_ANY_COL_ENBL 0x0800
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#define TX_16_COL_ENBL 0x8000
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/*
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* PP_TxCMD - Transmit Command bit definition - Read-only
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*/
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#define TX_START_4_BYTES 0x0000
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#define TX_START_64_BYTES 0x0040
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#define TX_START_128_BYTES 0x0080
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#define TX_START_ALL_BYTES 0x00C0
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#define TX_FORCE 0x0100
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#define TX_ONE_COL 0x0200
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#define TX_TWO_PART_DEFF_DISABLE 0x0400
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#define TX_NO_CRC 0x1000
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#define TX_RUNT 0x2000
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/*
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* PP_BufCFG - Buffer Configuration Interrupt Mask
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* bit definition - Read/write
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*/
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#define GENERATE_SW_INTERRUPT 0x0040
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#define RX_DMA_ENBL 0x0080
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#define READY_FOR_TX_ENBL 0x0100
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#define TX_UNDERRUN_ENBL 0x0200
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#define RX_MISS_ENBL 0x0400
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#define RX_128_BYTE_ENBL 0x0800
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#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
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#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
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#define RX_DEST_MATCH_ENBL 0x8000
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/*
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* PP_LineCTL - Line Control bit definition - Read/write
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*/
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#define SERIAL_RX_ON 0x0040
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#define SERIAL_TX_ON 0x0080
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#define AUI_ONLY 0x0100
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#define AUTO_AUI_10BASET 0x0200
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#define MODIFIED_BACKOFF 0x0800
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#define NO_AUTO_POLARITY 0x1000
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#define TWO_PART_DEFDIS 0x2000
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#define LOW_RX_SQUELCH 0x4000
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/*
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* PP_SelfCTL - Software Self Control bit definition - Read/write
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*/
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#define POWER_ON_RESET 0x0040
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#define SW_STOP 0x0100
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#define SLEEP_ON 0x0200
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#define AUTO_WAKEUP 0x0400
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#define HCB0_ENBL 0x1000
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#define HCB1_ENBL 0x2000
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#define HCB0 0x4000
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#define HCB1 0x8000
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/*
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* PP_BusCTL - ISA Bus Control bit definition - Read/write
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*/
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#define RESET_RX_DMA 0x0040
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#define MEMORY_ON 0x0400
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#define DMA_BURST_MODE 0x0800
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#define IO_CHANNEL_READY_ON 0x1000
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#define RX_DMA_SIZE_64Ks 0x2000
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#define ENABLE_IRQ 0x8000
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/*
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* PP_TestCTL - Test Control bit definition - Read/write
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*/
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#define LINK_OFF 0x0080
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#define ENDEC_LOOPBACK 0x0200
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#define AUI_LOOPBACK 0x0400
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#define BACKOFF_OFF 0x0800
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#define FAST_TEST 0x8000
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/*
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* PP_RxEvent - Receive Event Bit definition - Read-only
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*/
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#define RX_IA_HASHED 0x0040
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#define RX_DRIBBLE 0x0080
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#define RX_OK 0x0100
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#define RX_HASHED 0x0200
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#define RX_IA 0x0400
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#define RX_BROADCAST 0x0800
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#define RX_CRC_ERROR 0x1000
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#define RX_RUNT 0x2000
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#define RX_EXTRA_DATA 0x4000
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#define HASH_INDEX_MASK 0x0FC00
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/*
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* PP_TxEvent - Transmit Event Bit definition - Read-only
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*/
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#define TX_LOST_CRS 0x0040
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#define TX_SQE_ERROR 0x0080
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#define TX_OK 0x0100
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#define TX_LATE_COL 0x0200
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#define TX_JBR 0x0400
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#define TX_16_COL 0x8000
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#define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS)
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#define TX_COL_COUNT_MASK 0x7800
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/*
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* PP_BufEvent - Buffer Event Bit definition - Read-only
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*/
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#define SW_INTERRUPT 0x0040
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#define RX_DMA 0x0080
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#define READY_FOR_TX 0x0100
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#define TX_UNDERRUN 0x0200
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#define RX_MISS 0x0400
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#define RX_128_BYTE 0x0800
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#define TX_COL_OVRFLW 0x1000
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#define RX_MISS_OVRFLW 0x2000
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#define RX_DEST_MATCH 0x8000
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/*
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* PP_LineST - Ethernet Line Status bit definition - Read-only
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*/
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#define LINK_OK 0x0080
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#define AUI_ON 0x0100
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#define TENBASET_ON 0x0200
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#define POLARITY_OK 0x1000
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#define CRS_OK 0x4000
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/*
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* PP_SelfST - Chip Software Status bit definition
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*/
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#define ACTIVE_33V 0x0040
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#define INIT_DONE 0x0080
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#define SI_BUSY 0x0100
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#define EEPROM_PRESENT 0x0200
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#define EEPROM_OK 0x0400
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#define EL_PRESENT 0x0800
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#define EE_SIZE_64 0x1000
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/*
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* PP_BusST - ISA Bus Status bit definition
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*/
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#define TX_BID_ERROR 0x0080
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#define READY_FOR_TX_NOW 0x0100
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/*
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* PP_AutoNegCTL - Auto Negotiation Control bit definition
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*/
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#define RE_NEG_NOW 0x0040
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#define ALLOW_FDX 0x0080
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#define AUTO_NEG_ENABLE 0x0100
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#define NLP_ENABLE 0x0200
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#define FORCE_FDX 0x8000
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#define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE)
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#define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \
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ALLOW_FDX | RE_NEG_NOW)
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/*
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* PP_AutoNegST - Auto Negotiation Status bit definition
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*/
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#define AUTO_NEG_BUSY 0x0080
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#define FLP_LINK 0x0100
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#define FLP_LINK_GOOD 0x0800
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#define LINK_FAULT 0x1000
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#define HDX_ACTIVE 0x4000
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#define FDX_ACTIVE 0x8000
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/*
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* The following block defines the ISQ event types
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*/
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#define ISQ_RECEIVER_EVENT 0x04
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#define ISQ_TRANSMITTER_EVENT 0x08
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#define ISQ_BUFFER_EVENT 0x0c
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#define ISQ_RX_MISS_EVENT 0x10
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#define ISQ_TX_COL_EVENT 0x12
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#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
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#define ISQ_HIST 16 /* small history buffer */
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#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
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#define TXRXBUFSIZE 0x0600
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#define RXDMABUFSIZE 0x8000
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#define RXDMASIZE 0x4000
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#define TXRX_LENGTH_MASK 0x07FF
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/* rx options bits */
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#define RCV_WITH_RXON 1 /* Set SerRx ON */
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#define RCV_COUNTS 2 /* Use Framecnt1 */
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#define RCV_PONG 4 /* Pong respondent */
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#define RCV_DONG 8 /* Dong operation */
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#define RCV_POLLING 0x10 /* Poll RxEvent */
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#define RCV_ISQ 0x20 /* Use ISQ, int */
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#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
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#define RCV_DMA 0x200 /* Set RxDMA only */
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#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
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#define RCV_FIXED_DATA 0x800 /* Every frame same */
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#define RCV_IO 0x1000 /* Use ISA IO only */
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#define RCV_MEMORY 0x2000 /* Use ISA Memory */
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#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
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#define PKT_START PP_TxFrame /* Start of packet RAM */
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#define RX_FRAME_PORT 0x0000
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#define TX_FRAME_PORT RX_FRAME_PORT
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#define TX_CMD_PORT 0x0004
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#define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */
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#define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
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#define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */
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#define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */
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#define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
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#define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */
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#define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */
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#define TX_LEN_PORT 0x0006
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#define ISQ_PORT 0x0008
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#define ADD_PORT 0x000A
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#define DATA_PORT 0x000C
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#define EEPROM_WRITE_EN 0x00F0
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#define EEPROM_WRITE_DIS 0x0000
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#define EEPROM_WRITE_CMD 0x0100
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#define EEPROM_READ_CMD 0x0200
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/* Receive Header
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* Description of header of each packet in receive area of memory
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*/
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#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
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#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
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#define RBUF_LEN_LOW 2 /* Length of received data - low byte */
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#define RBUF_LEN_HI 3 /* Length of received data - high byte */
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#define RBUF_HEAD_LEN 4 /* Length of this header */
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#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
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#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
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/* for bios scan */
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/* */
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#ifdef CSDEBUG
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/* use these values for debugging bios scan */
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#define BIOS_START_SEG 0x00000
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#define BIOS_OFFSET_INC 0x0010
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#else
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#define BIOS_START_SEG 0x0c000
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#define BIOS_OFFSET_INC 0x0200
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#endif
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#define BIOS_LAST_OFFSET 0x0fc00
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/*
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* Word offsets into the EEPROM configuration buffer
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*/
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#define ISA_CNF_OFFSET 0x3
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#define INT_NO_MASK 0x000F
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#define DMA_NO_MASK 0x0070
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#define USE_SA 0x0080
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#define IOCHRDY_ENABLE 0x0100
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#define ISA_DMA_SIZE 0x0200 /* 0 16k 1 64k */
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#define ISA_AUTO_RxDMA 0x0400
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#define ISA_RxDMA 0x0800
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#define DMA_BURST 0x1000
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#define STREAM_TRANSFER 0x2000
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#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
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#define BOOT_PROM_FLAG 0x4000
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#define MEMORY_MODE 0x8000
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#define PACKET_PAGE_BASE (ISA_CNF_OFFSET + 1)
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#define BOOT_ROM_BASE (ISA_CNF_OFFSET + 2)
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#define BOOT_PROM_MASK (ISA_CNF_OFFSET + 3)
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#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 4) /* 8900 eeprom */
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#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 4) /* 8920 eeprom */
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/*
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* the assumption here is that the bits in the eeprom are generally
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* in the same position as those in the autonegctl register.
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* Of course the IMM bit is not in that register so it must be
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* masked out
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*/
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#define EE_FORCE_FDX 0x8000
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#define EE_NLP_ENABLE 0x0200
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#define EE_AUTO_NEG_ENABLE 0x0100
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#define EE_ALLOW_FDX 0x0080
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#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \
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EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX)
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#define IMM_BIT 0x0040 /* ignore missing media */
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#define ADAPTER_CNF_OFFSET (ISA_CNF_OFFSET + 5)
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#define A_CNF_MEDIA 0x0007
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#define A_CNF_10B_T 0x0001
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#define A_CNF_AUI 0x0002
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#define A_CNF_10B_2 0x0004
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#define A_CNF_MEDIA_TYPE 0x0060
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#define A_CNF_MEDIA_AUTO 0x0000
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#define A_CNF_MEDIA_10B_T 0x0020
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#define A_CNF_MEDIA_AUI 0x0040
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#define A_CNF_MEDIA_10B_2 0x0060
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#define A_CNF_DC_DC_POLARITY 0x0080
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#define A_CNF_WAKE_ENABLED 0x0100
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#define A_CNF_WAKE_CFG 0x0200
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#define A_CNF_CAN_WAKE 0x0400
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#define A_CNF_OPT_FLAGS 0x1800 /* 00 server, 01 DOS 10 multi-user */
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#define A_CNF_NO_AUTO_POLARITY 0x2000
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#define A_CNF_LOW_RX_SQUELCH 0x4000
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#define A_CNF_EXTND_10B_2 0x8000
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#define MFG_DATE_OFFSET (ISA_CNF_OFFSET + 8)
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#define PACKET_PAGE_OFFSET 0x8
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/* DMA controller registers */
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#define DMA_BASE 0x00 /* DMA controller base */
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#define DMA_BASE_2 0x0C0 /* DMA controller base */
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#define DMA_STAT 0x0D0 /* DMA controller status register */
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#define DMA_MASK 0x0D4 /* DMA controller mask register */
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#define DMA_MODE 0x0D6 /* DMA controller mode register */
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#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
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/* DMA data */
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#define DMA_DISABLE 0x04 /* Disable channel n */
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#define DMA_ENABLE 0x00 /* Enable channel n */
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/* Demand transfers, incr. address, auto init, writes, ch. n */
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#define DMA_RX_MODE 0x14
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/* Demand transfers, incr. address, auto init, reads, ch. n */
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#define DMA_TX_MODE 0x18
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#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
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#define CS8900 0x0000
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#define CS8920 0x4000
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#define CS8920M 0x6000
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#define REVISON_BITS 0x1F00
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#define EEVER_NUMBER 0x12
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#define CHKSUM_LEN 0x14
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#define CHKSUM_VAL 0x0000
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#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
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#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
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#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
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#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
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#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
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#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
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#define PNP_ADD_PORT 0x0279
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#define PNP_WRITE_PORT 0x0A79
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#define GET_PNP_ISA_STRUCT 0x40
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#define PNP_ISA_STRUCT_LEN 0x06
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#define PNP_CSN_CNT_OFF 0x01
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#define PNP_RD_PORT_OFF 0x02
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#define PNP_FUNCTION_OK 0x00
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#define PNP_WAKE 0x03
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#define PNP_RSRC_DATA 0x04
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#define PNP_RSRC_READY 0x01
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#define PNP_STATUS 0x05
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#define PNP_ACTIVATE 0x30
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#define PNP_CNF_IO_H 0x60
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#define PNP_CNF_IO_L 0x61
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#define PNP_CNF_INT 0x70
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#define PNP_CNF_DMA 0x74
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#define PNP_CNF_MEM 0x48
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#define BIT0 1
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#define BIT15 0x8000
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#define CS_DUPLEX_AUTO 0
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#define CS_DUPLEX_FULL 1
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#define CS_DUPLEX_HALF 2
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/*
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* It would appear that for pccards (well, the IBM EtherJet PCMCIA card) that
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* are connected to card bus bridges there's a problem. For reading the
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* value back you have to go into 8 bit mode. The Linux driver also uses
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* this trick. This may be a bug in the card and how it handles fast 16-bit
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* read after a write.
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*/
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#define HACK_FOR_CARDBUS_BRIDGE_PROBLEM
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#ifdef HACK_FOR_CARDBUS_BRIDGE_PROBLEM
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static __inline uint16_t
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cs_inw(struct cs_softc *sc, int off)
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{
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if (off & 1)
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device_printf(sc->dev, "BUG: inw to an odd address.\n");
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return ((inb(sc->nic_addr + off) & 0xff) |
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(inb(sc->nic_addr + off + 1) << 8));
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}
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#else
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static __inline uint16_t
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cs_inw(struct cs_softc *sc, int off)
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{
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return (inw(sc->nic_addr + off));
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}
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#endif
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static __inline void
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cs_outw(struct cs_softc *sc, int off, uint16_t val)
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{
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outw(sc->nic_addr + off, val);
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}
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static __inline uint16_t
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cs_readreg(struct cs_softc *sc, uint16_t port)
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|
{
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cs_outw(sc, ADD_PORT, port);
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return (cs_inw(sc, DATA_PORT));
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}
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static __inline void
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cs_writereg(struct cs_softc *sc, uint16_t port, uint16_t val)
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|
{
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cs_outw(sc, ADD_PORT, port);
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cs_outw(sc, DATA_PORT, val);
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}
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static __inline void
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|
reset_chip(struct cs_softc *sc)
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|
{
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|
cs_writereg(sc, PP_SelfCTL,
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cs_readreg(sc, PP_SelfCTL) | POWER_ON_RESET);
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|
}
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#define cs_duplex_full(sc) \
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(cs_writereg(sc, PP_AutoNegCTL, FORCE_FDX))
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#define cs_duplex_half(sc) \
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(cs_writereg(sc, PP_AutoNegCTL, NLP_ENABLE))
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|