f39e915e19
Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine. Approved by: gnn (mentor) MFC after: 3 days
309 lines
7.0 KiB
C
309 lines
7.0 KiB
C
/*-
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* Copyright (c) 2008 Joseph Koshy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Common code for handling Intel CPUs.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/cputypes.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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static int
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intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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(void) pc;
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PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
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pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS);
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/* allow the RDPMC instruction if needed */
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if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
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load_cr4(rcr4() | CR4_PCE);
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PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4());
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return 0;
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}
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static int
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intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
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{
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(void) pc;
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(void) pp; /* can be NULL */
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PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp,
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(uintmax_t) rcr4());
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/* always turn off the RDPMC instruction */
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load_cr4(rcr4() & ~CR4_PCE);
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return 0;
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}
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struct pmc_mdep *
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pmc_intel_initialize(void)
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{
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struct pmc_mdep *pmc_mdep;
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enum pmc_cputype cputype;
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int error, model, nclasses, ncpus;
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KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
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("[intel,%d] Initializing non-intel processor", __LINE__));
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PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);
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cputype = -1;
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nclasses = 2;
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model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4);
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switch (cpu_id & 0xF00) {
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#if defined(__i386__)
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case 0x500: /* Pentium family processors */
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cputype = PMC_CPU_INTEL_P5;
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break;
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#endif
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case 0x600: /* Pentium Pro, Celeron, Pentium II & III */
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switch (model) {
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#if defined(__i386__)
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case 0x1:
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cputype = PMC_CPU_INTEL_P6;
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break;
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case 0x3: case 0x5:
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cputype = PMC_CPU_INTEL_PII;
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break;
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case 0x6: case 0x16:
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cputype = PMC_CPU_INTEL_CL;
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break;
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case 0x7: case 0x8: case 0xA: case 0xB:
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cputype = PMC_CPU_INTEL_PIII;
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break;
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case 0x9: case 0xD:
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cputype = PMC_CPU_INTEL_PM;
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break;
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#endif
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case 0xE:
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cputype = PMC_CPU_INTEL_CORE;
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break;
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case 0xF:
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cputype = PMC_CPU_INTEL_CORE2;
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nclasses = 3;
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break;
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case 0x17:
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cputype = PMC_CPU_INTEL_CORE2EXTREME;
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nclasses = 3;
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break;
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case 0x1C: /* Per Intel document 320047-002. */
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cputype = PMC_CPU_INTEL_ATOM;
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nclasses = 3;
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break;
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case 0x1A:
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case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
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case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */
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case 0x2E:
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cputype = PMC_CPU_INTEL_COREI7;
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nclasses = 5;
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break;
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case 0x25: /* Per Intel document 253669-033US 12/2009. */
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case 0x2C: /* Per Intel document 253669-033US 12/2009. */
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cputype = PMC_CPU_INTEL_WESTMERE;
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nclasses = 5;
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break;
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case 0x2A: /* Per Intel document 253669-039US 05/2011. */
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cputype = PMC_CPU_INTEL_SANDYBRIDGE;
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nclasses = 5;
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break;
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}
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break;
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#if defined(__i386__) || defined(__amd64__)
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case 0xF00: /* P4 */
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if (model >= 0 && model <= 6) /* known models */
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cputype = PMC_CPU_INTEL_PIV;
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break;
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}
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#endif
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if ((int) cputype == -1) {
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printf("pmc: Unknown Intel CPU.\n");
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return (NULL);
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}
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/* Allocate base class and initialize machine dependent struct */
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pmc_mdep = pmc_mdep_alloc(nclasses);
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pmc_mdep->pmd_cputype = cputype;
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pmc_mdep->pmd_switch_in = intel_switch_in;
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pmc_mdep->pmd_switch_out = intel_switch_out;
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ncpus = pmc_cpu_max();
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error = pmc_tsc_initialize(pmc_mdep, ncpus);
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if (error)
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goto error;
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switch (cputype) {
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#if defined(__i386__) || defined(__amd64__)
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/*
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* Intel Core, Core 2 and Atom processors.
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*/
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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error = pmc_core_initialize(pmc_mdep, ncpus);
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break;
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/*
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* Intel Pentium 4 Processors, and P4/EMT64 processors.
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*/
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case PMC_CPU_INTEL_PIV:
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error = pmc_p4_initialize(pmc_mdep, ncpus);
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break;
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#endif
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#if defined(__i386__)
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/*
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* P6 Family Processors
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*/
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case PMC_CPU_INTEL_P6:
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case PMC_CPU_INTEL_CL:
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case PMC_CPU_INTEL_PII:
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case PMC_CPU_INTEL_PIII:
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case PMC_CPU_INTEL_PM:
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error = pmc_p6_initialize(pmc_mdep, ncpus);
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break;
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/*
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* Intel Pentium PMCs.
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*/
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case PMC_CPU_INTEL_P5:
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error = pmc_p5_initialize(pmc_mdep, ncpus);
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break;
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#endif
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default:
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KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__));
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}
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if (error)
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goto error;
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/*
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* Init the uncore class.
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*/
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#if defined(__i386__) || defined(__amd64__)
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switch (cputype) {
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/*
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* Intel Corei7 and Westmere processors.
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*/
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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error = pmc_uncore_initialize(pmc_mdep, ncpus);
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break;
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default:
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break;
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}
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#endif
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error:
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if (error) {
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free(pmc_mdep, M_PMC);
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pmc_mdep = NULL;
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}
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return (pmc_mdep);
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}
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void
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pmc_intel_finalize(struct pmc_mdep *md)
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{
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pmc_tsc_finalize(md);
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switch (md->pmd_cputype) {
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#if defined(__i386__) || defined(__amd64__)
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case PMC_CPU_INTEL_ATOM:
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case PMC_CPU_INTEL_CORE:
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case PMC_CPU_INTEL_CORE2:
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case PMC_CPU_INTEL_CORE2EXTREME:
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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pmc_core_finalize(md);
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break;
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case PMC_CPU_INTEL_PIV:
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pmc_p4_finalize(md);
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break;
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#endif
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#if defined(__i386__)
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case PMC_CPU_INTEL_P6:
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case PMC_CPU_INTEL_CL:
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case PMC_CPU_INTEL_PII:
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case PMC_CPU_INTEL_PIII:
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case PMC_CPU_INTEL_PM:
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pmc_p6_finalize(md);
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break;
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case PMC_CPU_INTEL_P5:
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pmc_p5_finalize(md);
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break;
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#endif
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default:
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KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__));
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}
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/*
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* Uncore.
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*/
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#if defined(__i386__) || defined(__amd64__)
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switch (md->pmd_cputype) {
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case PMC_CPU_INTEL_COREI7:
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case PMC_CPU_INTEL_SANDYBRIDGE:
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case PMC_CPU_INTEL_WESTMERE:
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pmc_uncore_finalize(md);
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break;
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default:
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break;
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}
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#endif
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}
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