b8aa843c63
- Split core DRM routines back into their own module, rather than using the nasty templated system like before. - Development-class R300 support in radeon driver (requires userland pieces, of course). - Mach64 driver (haven't tested in a while -- my mach64s no longer fit in the testbox). Covers Rage Pros, Rage Mobility P/M, Rage XL, and some others. - i915 driver files, which just need to get drm_drv.c fixed to allow attachment to the drmsub device. Covers i830 through i915 integrated graphics. - savage driver files, which should require minimal changes to work. Covers the Savage3D, Savage IX/MX, Savage 4, ProSavage. - Support for color and texture tiling and HyperZ features of Radeon. Thanks to: scottl (much p4 handholding) Jung-uk Kim (helpful prodding) PR: [1] kern/76879, [2] kern/72548 Submitted by: [1] Alex, lesha at intercaf dot ru [2] Shaun Jurrens, shaun at shamz dot net
654 lines
24 KiB
C
654 lines
24 KiB
C
/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- */
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/*-
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* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
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* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Kevin E. Martin <martin@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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* $FreeBSD$
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*/
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#ifndef __RADEON_DRM_H__
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#define __RADEON_DRM_H__
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the X server file (radeon_sarea.h)
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*/
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#ifndef __RADEON_SAREA_DEFINES__
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#define __RADEON_SAREA_DEFINES__
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/* Old style state flags, required for sarea interface (1.1 and 1.2
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* clears) and 1.2 drm_vertex2 ioctl.
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*/
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#define RADEON_UPLOAD_CONTEXT 0x00000001
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#define RADEON_UPLOAD_VERTFMT 0x00000002
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#define RADEON_UPLOAD_LINE 0x00000004
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#define RADEON_UPLOAD_BUMPMAP 0x00000008
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#define RADEON_UPLOAD_MASKS 0x00000010
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#define RADEON_UPLOAD_VIEWPORT 0x00000020
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#define RADEON_UPLOAD_SETUP 0x00000040
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#define RADEON_UPLOAD_TCL 0x00000080
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#define RADEON_UPLOAD_MISC 0x00000100
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#define RADEON_UPLOAD_TEX0 0x00000200
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#define RADEON_UPLOAD_TEX1 0x00000400
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#define RADEON_UPLOAD_TEX2 0x00000800
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#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
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#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
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#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
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#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
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#define RADEON_REQUIRE_QUIESCENCE 0x00010000
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#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
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#define RADEON_UPLOAD_ALL 0x003effff
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#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
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/* New style per-packet identifiers for use in cmd_buffer ioctl with
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* the RADEON_EMIT_PACKET command. Comments relate new packets to old
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* state bits and the packet size:
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*/
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#define RADEON_EMIT_PP_MISC 0 /* context/7 */
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#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
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#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
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#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
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#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
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#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
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#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
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#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
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#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
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#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
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#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
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#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
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#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
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#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
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#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
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#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
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#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
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#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
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#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
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#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
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#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
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#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
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#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
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#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
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#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
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#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
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#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
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#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
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#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
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#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
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#define R200_EMIT_VAP_CTL 32 /* vap/1 */
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#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
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#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
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#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
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#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
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#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
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#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
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#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
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#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
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#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
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#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
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#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
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#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
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#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
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#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
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#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
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#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
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#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
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#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
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#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
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#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
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#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
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#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
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#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
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#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
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#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
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#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
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#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
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#define R200_EMIT_PP_CUBIC_FACES_0 61
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#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
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#define R200_EMIT_PP_CUBIC_FACES_1 63
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#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
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#define R200_EMIT_PP_CUBIC_FACES_2 65
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#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
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#define R200_EMIT_PP_CUBIC_FACES_3 67
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#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
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#define R200_EMIT_PP_CUBIC_FACES_4 69
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#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
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#define R200_EMIT_PP_CUBIC_FACES_5 71
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#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
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#define RADEON_EMIT_PP_TEX_SIZE_0 73
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#define RADEON_EMIT_PP_TEX_SIZE_1 74
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#define RADEON_EMIT_PP_TEX_SIZE_2 75
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#define R200_EMIT_RB3D_BLENDCOLOR 76
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#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
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#define RADEON_EMIT_PP_CUBIC_FACES_0 78
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
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#define RADEON_EMIT_PP_CUBIC_FACES_1 80
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
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#define RADEON_EMIT_PP_CUBIC_FACES_2 82
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#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
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#define R200_EMIT_PP_TRI_PERF_CNTL 84
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#define RADEON_MAX_STATE_PACKETS 85
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/* Commands understood by cmd_buffer ioctl. More can be added but
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* obviously these can't be removed or changed:
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*/
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#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
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#define RADEON_CMD_SCALARS 2 /* emit scalar data */
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#define RADEON_CMD_VECTORS 3 /* emit vector data */
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#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
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#define RADEON_CMD_PACKET3 5 /* emit hw packet */
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#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
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#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
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#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
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* doesn't make the cpu wait, just
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* the graphics hardware */
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typedef union {
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int i;
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struct {
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unsigned char cmd_type, pad0, pad1, pad2;
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} header;
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struct {
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unsigned char cmd_type, packet_id, pad0, pad1;
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} packet;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} scalars;
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struct {
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unsigned char cmd_type, offset, stride, count;
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} vectors;
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struct {
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unsigned char cmd_type, buf_idx, pad0, pad1;
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} dma;
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struct {
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unsigned char cmd_type, flags, pad0, pad1;
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} wait;
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} drm_radeon_cmd_header_t;
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#define RADEON_WAIT_2D 0x1
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#define RADEON_WAIT_3D 0x2
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#define RADEON_FRONT 0x1
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#define RADEON_BACK 0x2
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#define RADEON_DEPTH 0x4
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#define RADEON_STENCIL 0x8
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#define RADEON_CLEAR_FASTZ 0x80000000
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#define RADEON_USE_HIERZ 0x40000000
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#define RADEON_USE_COMP_ZBUF 0x20000000
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/* Primitive types
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*/
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#define RADEON_POINTS 0x1
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#define RADEON_LINES 0x2
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#define RADEON_LINE_STRIP 0x3
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#define RADEON_TRIANGLES 0x4
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#define RADEON_TRIANGLE_FAN 0x5
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#define RADEON_TRIANGLE_STRIP 0x6
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/* Vertex/indirect buffer size
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*/
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#define RADEON_BUFFER_SIZE 65536
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/* Byte offsets for indirect buffer data
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*/
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#define RADEON_INDEX_PRIM_OFFSET 20
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#define RADEON_SCRATCH_REG_OFFSET 32
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#define RADEON_NR_SAREA_CLIPRECTS 12
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/* There are 2 heaps (local/GART). Each region within a heap is a
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* minimum of 64k, and there are at most 64 of them per heap.
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*/
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#define RADEON_LOCAL_TEX_HEAP 0
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#define RADEON_GART_TEX_HEAP 1
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#define RADEON_NR_TEX_HEAPS 2
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#define RADEON_NR_TEX_REGIONS 64
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#define RADEON_LOG_TEX_GRANULARITY 16
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#define RADEON_MAX_TEXTURE_LEVELS 12
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#define RADEON_MAX_TEXTURE_UNITS 3
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#define RADEON_MAX_SURFACES 8
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/* Blits have strict offset rules. All blit offset must be aligned on
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* a 1K-byte boundary.
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*/
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#define RADEON_OFFSET_SHIFT 10
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#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
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#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
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#endif /* __RADEON_SAREA_DEFINES__ */
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typedef struct {
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unsigned int red;
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unsigned int green;
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unsigned int blue;
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unsigned int alpha;
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} radeon_color_regs_t;
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typedef struct {
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/* Context state */
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unsigned int pp_misc; /* 0x1c14 */
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unsigned int pp_fog_color;
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unsigned int re_solid_color;
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unsigned int rb3d_blendcntl;
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unsigned int rb3d_depthoffset;
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unsigned int rb3d_depthpitch;
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unsigned int rb3d_zstencilcntl;
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unsigned int pp_cntl; /* 0x1c38 */
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unsigned int rb3d_cntl;
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unsigned int rb3d_coloroffset;
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unsigned int re_width_height;
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unsigned int rb3d_colorpitch;
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unsigned int se_cntl;
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/* Vertex format state */
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unsigned int se_coord_fmt; /* 0x1c50 */
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/* Line state */
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unsigned int re_line_pattern; /* 0x1cd0 */
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unsigned int re_line_state;
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unsigned int se_line_width; /* 0x1db8 */
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/* Bumpmap state */
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unsigned int pp_lum_matrix; /* 0x1d00 */
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unsigned int pp_rot_matrix_0; /* 0x1d58 */
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unsigned int pp_rot_matrix_1;
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/* Mask state */
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unsigned int rb3d_stencilrefmask; /* 0x1d7c */
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unsigned int rb3d_ropcntl;
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unsigned int rb3d_planemask;
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/* Viewport state */
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unsigned int se_vport_xscale; /* 0x1d98 */
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unsigned int se_vport_xoffset;
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unsigned int se_vport_yscale;
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unsigned int se_vport_yoffset;
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unsigned int se_vport_zscale;
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unsigned int se_vport_zoffset;
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/* Setup state */
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unsigned int se_cntl_status; /* 0x2140 */
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/* Misc state */
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unsigned int re_top_left; /* 0x26c0 */
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unsigned int re_misc;
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} drm_radeon_context_regs_t;
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typedef struct {
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/* Zbias state */
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unsigned int se_zbias_factor; /* 0x1dac */
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unsigned int se_zbias_constant;
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} drm_radeon_context2_regs_t;
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/* Setup registers for each texture unit
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*/
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typedef struct {
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unsigned int pp_txfilter;
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unsigned int pp_txformat;
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unsigned int pp_txoffset;
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unsigned int pp_txcblend;
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unsigned int pp_txablend;
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unsigned int pp_tfactor;
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unsigned int pp_border_color;
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} drm_radeon_texture_regs_t;
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typedef struct {
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unsigned int start;
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unsigned int finish;
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unsigned int prim:8;
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unsigned int stateidx:8;
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unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
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unsigned int vc_format; /* vertex format */
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} drm_radeon_prim_t;
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typedef struct {
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drm_radeon_context_regs_t context;
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drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
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drm_radeon_context2_regs_t context2;
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unsigned int dirty;
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} drm_radeon_state_t;
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typedef struct {
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/* The channel for communication of state information to the
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* kernel on firing a vertex buffer with either of the
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* obsoleted vertex/index ioctls.
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*/
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drm_radeon_context_regs_t context_state;
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drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
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unsigned int dirty;
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unsigned int vertsize;
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unsigned int vc_format;
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/* The current cliprects, or a subset thereof.
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*/
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drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
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unsigned int nbox;
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/* Counters for client-side throttling of rendering clients.
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*/
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unsigned int last_frame;
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unsigned int last_dispatch;
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unsigned int last_clear;
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drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
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1];
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unsigned int tex_age[RADEON_NR_TEX_HEAPS];
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int ctx_owner;
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int pfState; /* number of 3d windows (0,1,2ormore) */
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int pfCurrentPage; /* which buffer is being displayed? */
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int crtc2_base; /* CRTC2 frame offset */
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int tiling_enabled; /* set by drm, read by 2d + 3d clients */
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} drm_radeon_sarea_t;
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (xf86drmRadeon.h)
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*
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* KW: actually it's illegal to change any of this (backwards compatibility).
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*/
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/* Radeon specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_RADEON_CP_INIT 0x00
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#define DRM_RADEON_CP_START 0x01
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#define DRM_RADEON_CP_STOP 0x02
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#define DRM_RADEON_CP_RESET 0x03
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#define DRM_RADEON_CP_IDLE 0x04
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#define DRM_RADEON_RESET 0x05
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#define DRM_RADEON_FULLSCREEN 0x06
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#define DRM_RADEON_SWAP 0x07
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#define DRM_RADEON_CLEAR 0x08
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#define DRM_RADEON_VERTEX 0x09
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#define DRM_RADEON_INDICES 0x0A
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#define DRM_RADEON_NOT_USED
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#define DRM_RADEON_STIPPLE 0x0C
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#define DRM_RADEON_INDIRECT 0x0D
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#define DRM_RADEON_TEXTURE 0x0E
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#define DRM_RADEON_VERTEX2 0x0F
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#define DRM_RADEON_CMDBUF 0x10
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#define DRM_RADEON_GETPARAM 0x11
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#define DRM_RADEON_FLIP 0x12
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#define DRM_RADEON_ALLOC 0x13
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#define DRM_RADEON_FREE 0x14
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#define DRM_RADEON_INIT_HEAP 0x15
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#define DRM_RADEON_IRQ_EMIT 0x16
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#define DRM_RADEON_IRQ_WAIT 0x17
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#define DRM_RADEON_CP_RESUME 0x18
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#define DRM_RADEON_SETPARAM 0x19
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#define DRM_RADEON_SURF_ALLOC 0x1a
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#define DRM_RADEON_SURF_FREE 0x1b
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
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#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
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#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
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#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
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#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
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#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
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#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
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#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
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#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
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#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
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#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
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#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
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#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
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#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
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#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
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#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
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#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
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#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
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#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
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#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
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#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
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#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
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#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
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#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
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#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
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#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
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typedef struct drm_radeon_init {
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enum {
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RADEON_INIT_CP = 0x01,
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RADEON_CLEANUP_CP = 0x02,
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RADEON_INIT_R200_CP = 0x03,
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RADEON_INIT_R300_CP = 0x04
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} func;
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unsigned long sarea_priv_offset;
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int is_pci; /* not used, driver asks hardware */
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int cp_mode;
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int gart_size;
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int ring_size;
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int usec_timeout;
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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unsigned long fb_offset;
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unsigned long mmio_offset;
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unsigned long ring_offset;
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unsigned long ring_rptr_offset;
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unsigned long buffers_offset;
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unsigned long gart_textures_offset;
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} drm_radeon_init_t;
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typedef struct drm_radeon_cp_stop {
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int flush;
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int idle;
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} drm_radeon_cp_stop_t;
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typedef struct drm_radeon_fullscreen {
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enum {
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RADEON_INIT_FULLSCREEN = 0x01,
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RADEON_CLEANUP_FULLSCREEN = 0x02
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} func;
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} drm_radeon_fullscreen_t;
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#define CLEAR_X1 0
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#define CLEAR_Y1 1
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#define CLEAR_X2 2
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#define CLEAR_Y2 3
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#define CLEAR_DEPTH 4
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typedef union drm_radeon_clear_rect {
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float f[5];
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unsigned int ui[5];
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} drm_radeon_clear_rect_t;
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typedef struct drm_radeon_clear {
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unsigned int flags;
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unsigned int clear_color;
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unsigned int clear_depth;
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unsigned int color_mask;
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unsigned int depth_mask; /* misnamed field: should be stencil */
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drm_radeon_clear_rect_t __user *depth_boxes;
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} drm_radeon_clear_t;
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typedef struct drm_radeon_vertex {
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int prim;
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int idx; /* Index of vertex buffer */
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int count; /* Number of vertices in buffer */
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int discard; /* Client finished with buffer? */
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} drm_radeon_vertex_t;
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typedef struct drm_radeon_indices {
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int prim;
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int idx;
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int start;
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int end;
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int discard; /* Client finished with buffer? */
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} drm_radeon_indices_t;
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/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
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* - allows multiple primitives and state changes in a single ioctl
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* - supports driver change to emit native primitives
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*/
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typedef struct drm_radeon_vertex2 {
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int idx; /* Index of vertex buffer */
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int discard; /* Client finished with buffer? */
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int nr_states;
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drm_radeon_state_t __user *state;
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int nr_prims;
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drm_radeon_prim_t __user *prim;
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} drm_radeon_vertex2_t;
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/* v1.3 - obsoletes drm_radeon_vertex2
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* - allows arbitarily large cliprect list
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* - allows updating of tcl packet, vector and scalar state
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* - allows memory-efficient description of state updates
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* - allows state to be emitted without a primitive
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* (for clears, ctx switches)
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* - allows more than one dma buffer to be referenced per ioctl
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* - supports tcl driver
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* - may be extended in future versions with new cmd types, packets
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*/
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typedef struct drm_radeon_cmd_buffer {
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int bufsz;
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char __user *buf;
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int nbox;
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drm_clip_rect_t __user *boxes;
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} drm_radeon_cmd_buffer_t;
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typedef struct drm_radeon_tex_image {
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unsigned int x, y; /* Blit coordinates */
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unsigned int width, height;
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const void __user *data;
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} drm_radeon_tex_image_t;
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typedef struct drm_radeon_texture {
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unsigned int offset;
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int pitch;
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int format;
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int width; /* Texture image coordinates */
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int height;
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drm_radeon_tex_image_t __user *image;
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} drm_radeon_texture_t;
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typedef struct drm_radeon_stipple {
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unsigned int __user *mask;
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} drm_radeon_stipple_t;
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typedef struct drm_radeon_indirect {
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int idx;
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int start;
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int end;
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int discard;
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} drm_radeon_indirect_t;
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/* 1.3: An ioctl to get parameters that aren't available to the 3d
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* client any other way.
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*/
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#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
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#define RADEON_PARAM_LAST_FRAME 2
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#define RADEON_PARAM_LAST_DISPATCH 3
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#define RADEON_PARAM_LAST_CLEAR 4
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/* Added with DRM version 1.6. */
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#define RADEON_PARAM_IRQ_NR 5
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#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
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/* Added with DRM version 1.8. */
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#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
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#define RADEON_PARAM_STATUS_HANDLE 8
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#define RADEON_PARAM_SAREA_HANDLE 9
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#define RADEON_PARAM_GART_TEX_HANDLE 10
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#define RADEON_PARAM_SCRATCH_OFFSET 11
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typedef struct drm_radeon_getparam {
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int param;
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void __user *value;
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} drm_radeon_getparam_t;
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/* 1.6: Set up a memory manager for regions of shared memory:
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*/
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#define RADEON_MEM_REGION_GART 1
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#define RADEON_MEM_REGION_FB 2
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typedef struct drm_radeon_mem_alloc {
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int region;
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int alignment;
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int size;
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int __user *region_offset; /* offset from start of fb or GART */
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} drm_radeon_mem_alloc_t;
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typedef struct drm_radeon_mem_free {
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int region;
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int region_offset;
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} drm_radeon_mem_free_t;
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typedef struct drm_radeon_mem_init_heap {
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int region;
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int size;
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int start;
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} drm_radeon_mem_init_heap_t;
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|
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/* 1.6: Userspace can request & wait on irq's:
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*/
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typedef struct drm_radeon_irq_emit {
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int __user *irq_seq;
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} drm_radeon_irq_emit_t;
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typedef struct drm_radeon_irq_wait {
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int irq_seq;
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} drm_radeon_irq_wait_t;
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/* 1.10: Clients tell the DRM where they think the framebuffer is located in
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|
* the card's address space, via a new generic ioctl to set parameters
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*/
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typedef struct drm_radeon_setparam {
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unsigned int param;
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int64_t value;
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} drm_radeon_setparam_t;
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|
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#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
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#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
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|
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/* 1.14: Clients can allocate/free a surface
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*/
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typedef struct drm_radeon_surface_alloc {
|
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unsigned int address;
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unsigned int size;
|
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unsigned int flags;
|
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} drm_radeon_surface_alloc_t;
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|
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typedef struct drm_radeon_surface_free {
|
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unsigned int address;
|
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} drm_radeon_surface_free_t;
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#endif
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