b74b94d2a1
We use to handle each message separately in i2c_transfer but that cannot work with message with NOSTOP as it confuses the controller that we disable the interrupts and start a new message. Handle every message in the interrupt handler and fire a new start condition if the previous message have NOSTOP, the controller understand this as a repeated start. This fixes booting on Allwinner A10/A20 platform where before the i2c controller used to write 0 to the PMIC register that control the regulators as it though that this was the continuation of the write message. Tested on: A20 BananaPi, Cubieboard 1 (kevans) Reported by: kevans MFC after: 1 month
754 lines
19 KiB
C
754 lines
19 KiB
C
/*-
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for the TWSI (aka I2C, aka IIC) bus controller found on Marvell
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* and Allwinner SoCs. Supports master operation only.
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*
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* Calls to DELAY() are needed per Application Note AN-179 "TWSI Software
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* Guidelines for Discovery(TM), Horizon (TM) and Feroceon(TM) Devices".
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <machine/_inttypes.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/iicbus/twsi/twsi.h>
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#include "iicbus_if.h"
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#define TWSI_CONTROL_ACK (1 << 2)
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#define TWSI_CONTROL_IFLG (1 << 3)
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#define TWSI_CONTROL_STOP (1 << 4)
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#define TWSI_CONTROL_START (1 << 5)
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#define TWSI_CONTROL_TWSIEN (1 << 6)
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#define TWSI_CONTROL_INTEN (1 << 7)
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#define TWSI_STATUS_START 0x08
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#define TWSI_STATUS_RPTD_START 0x10
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#define TWSI_STATUS_ADDR_W_ACK 0x18
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#define TWSI_STATUS_ADDR_W_NACK 0x20
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#define TWSI_STATUS_DATA_WR_ACK 0x28
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#define TWSI_STATUS_DATA_WR_NACK 0x30
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#define TWSI_STATUS_ADDR_R_ACK 0x40
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#define TWSI_STATUS_ADDR_R_NACK 0x48
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#define TWSI_STATUS_DATA_RD_ACK 0x50
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#define TWSI_STATUS_DATA_RD_NOACK 0x58
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#define TWSI_DEBUG
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#undef TWSI_DEBUG
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#ifdef TWSI_DEBUG
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#define debugf(dev, fmt, args...) device_printf(dev, "%s: " fmt, __func__, ##args)
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#else
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#define debugf(dev, fmt, args...)
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#endif
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static struct resource_spec res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
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{ -1, 0 }
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};
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static __inline uint32_t
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TWSI_READ(struct twsi_softc *sc, bus_size_t off)
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{
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uint32_t val;
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val = bus_read_4(sc->res[0], off);
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debugf(sc->dev, "read %x from %lx\n", val, off);
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return (val);
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}
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static __inline void
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TWSI_WRITE(struct twsi_softc *sc, bus_size_t off, uint32_t val)
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{
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debugf(sc->dev, "Writing %x to %lx\n", val, off);
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bus_write_4(sc->res[0], off, val);
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}
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static __inline void
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twsi_control_clear(struct twsi_softc *sc, uint32_t mask)
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{
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uint32_t val;
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val = TWSI_READ(sc, sc->reg_control);
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debugf(sc->dev, "read val=%x\n", val);
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val &= ~(TWSI_CONTROL_STOP | TWSI_CONTROL_START);
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val &= ~mask;
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debugf(sc->dev, "write val=%x\n", val);
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TWSI_WRITE(sc, sc->reg_control, val);
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}
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static __inline void
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twsi_control_set(struct twsi_softc *sc, uint32_t mask)
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{
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uint32_t val;
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val = TWSI_READ(sc, sc->reg_control);
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debugf(sc->dev, "read val=%x\n", val);
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val &= ~(TWSI_CONTROL_STOP | TWSI_CONTROL_START);
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val |= mask;
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debugf(sc->dev, "write val=%x\n", val);
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TWSI_WRITE(sc, sc->reg_control, val);
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}
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static __inline void
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twsi_clear_iflg(struct twsi_softc *sc)
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{
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DELAY(1000);
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twsi_control_clear(sc, TWSI_CONTROL_IFLG);
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DELAY(1000);
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}
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/*
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* timeout given in us
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* returns
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* 0 on successful mask change
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* non-zero on timeout
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*/
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static int
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twsi_poll_ctrl(struct twsi_softc *sc, int timeout, uint32_t mask)
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{
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timeout /= 10;
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debugf(sc->dev, "Waiting for ctrl reg to match mask %x\n", mask);
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while (!(TWSI_READ(sc, sc->reg_control) & mask)) {
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DELAY(10);
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if (--timeout < 0)
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return (timeout);
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}
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debugf(sc->dev, "done\n");
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return (0);
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}
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/*
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* 'timeout' is given in us. Note also that timeout handling is not exact --
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* twsi_locked_start() total wait can be more than 2 x timeout
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* (twsi_poll_ctrl() is called twice). 'mask' can be either TWSI_STATUS_START
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* or TWSI_STATUS_RPTD_START
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*/
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static int
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twsi_locked_start(device_t dev, struct twsi_softc *sc, int32_t mask,
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u_char slave, int timeout)
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{
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int read_access, iflg_set = 0;
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uint32_t status;
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mtx_assert(&sc->mutex, MA_OWNED);
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if (mask == TWSI_STATUS_RPTD_START)
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/* read IFLG to know if it should be cleared later; from NBSD */
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iflg_set = TWSI_READ(sc, sc->reg_control) & TWSI_CONTROL_IFLG;
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debugf(dev, "send start\n");
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twsi_control_set(sc, TWSI_CONTROL_START);
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if (mask == TWSI_STATUS_RPTD_START && iflg_set) {
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debugf(dev, "IFLG set, clearing (mask=%x)\n", mask);
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twsi_clear_iflg(sc);
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}
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/*
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* Without this delay we timeout checking IFLG if the timeout is 0.
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* NBSD driver always waits here too.
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*/
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DELAY(1000);
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if (twsi_poll_ctrl(sc, timeout, TWSI_CONTROL_IFLG)) {
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debugf(dev, "timeout sending %sSTART condition\n",
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mask == TWSI_STATUS_START ? "" : "repeated ");
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return (IIC_ETIMEOUT);
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}
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status = TWSI_READ(sc, sc->reg_status);
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debugf(dev, "status=%x\n", status);
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if (status != mask) {
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debugf(dev, "wrong status (%02x) after sending %sSTART condition\n",
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status, mask == TWSI_STATUS_START ? "" : "repeated ");
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return (IIC_ESTATUS);
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}
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TWSI_WRITE(sc, sc->reg_data, slave);
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twsi_clear_iflg(sc);
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DELAY(1000);
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if (twsi_poll_ctrl(sc, timeout, TWSI_CONTROL_IFLG)) {
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debugf(dev, "timeout sending slave address (timeout=%d)\n", timeout);
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return (IIC_ETIMEOUT);
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}
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read_access = (slave & 0x1) ? 1 : 0;
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status = TWSI_READ(sc, sc->reg_status);
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if (status != (read_access ?
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TWSI_STATUS_ADDR_R_ACK : TWSI_STATUS_ADDR_W_ACK)) {
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debugf(dev, "no ACK (status: %02x) after sending slave address\n",
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status);
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return (IIC_ENOACK);
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}
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return (IIC_NOERR);
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}
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#ifdef EXT_RESOURCES
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#define TWSI_BAUD_RATE_RAW(C,M,N) ((C)/((10*(M+1))<<(N)))
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#define ABSSUB(a,b) (((a) > (b)) ? (a) - (b) : (b) - (a))
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static int
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twsi_calc_baud_rate(struct twsi_softc *sc, const u_int target,
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int *param)
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{
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uint64_t clk;
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uint32_t cur, diff, diff0;
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int m, n, m0, n0;
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/* Calculate baud rate. */
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diff0 = 0xffffffff;
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if (clk_get_freq(sc->clk_core, &clk) < 0)
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return (-1);
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debugf(sc->dev, "Bus clock is at %ju\n", clk);
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for (n = 0; n < 8; n++) {
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for (m = 0; m < 16; m++) {
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cur = TWSI_BAUD_RATE_RAW(clk,m,n);
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diff = ABSSUB(target, cur);
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if (diff < diff0) {
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m0 = m;
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n0 = n;
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diff0 = diff;
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}
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}
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}
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*param = TWSI_BAUD_RATE_PARAM(m0, n0);
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return (0);
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}
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#endif /* EXT_RESOURCES */
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/*
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* Only slave mode supported, disregard [old]addr
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*/
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static int
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twsi_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct twsi_softc *sc;
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uint32_t param;
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#ifdef EXT_RESOURCES
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u_int busfreq;
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#endif
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sc = device_get_softc(dev);
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#ifdef EXT_RESOURCES
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busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
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if (twsi_calc_baud_rate(sc, busfreq, ¶m) == -1) {
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#endif
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switch (speed) {
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case IIC_SLOW:
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case IIC_FAST:
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param = sc->baud_rate[speed].param;
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debugf(dev, "Using IIC_FAST mode with speed param=%x\n", param);
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break;
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case IIC_FASTEST:
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case IIC_UNKNOWN:
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default:
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param = sc->baud_rate[IIC_FAST].param;
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debugf(dev, "Using IIC_FASTEST/UNKNOWN mode with speed param=%x\n", param);
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break;
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}
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#ifdef EXT_RESOURCES
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}
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#endif
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debugf(dev, "Using clock param=%x\n", param);
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mtx_lock(&sc->mutex);
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TWSI_WRITE(sc, sc->reg_soft_reset, 0x0);
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TWSI_WRITE(sc, sc->reg_baud_rate, param);
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TWSI_WRITE(sc, sc->reg_control, TWSI_CONTROL_TWSIEN);
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DELAY(1000);
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mtx_unlock(&sc->mutex);
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return (0);
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}
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static int
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twsi_stop(device_t dev)
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{
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struct twsi_softc *sc;
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sc = device_get_softc(dev);
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debugf(dev, "%s\n", __func__);
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mtx_lock(&sc->mutex);
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twsi_control_clear(sc, TWSI_CONTROL_ACK);
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twsi_control_set(sc, TWSI_CONTROL_STOP);
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twsi_clear_iflg(sc);
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DELAY(1000);
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mtx_unlock(&sc->mutex);
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return (IIC_NOERR);
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}
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/*
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* timeout is given in us
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*/
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static int
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twsi_repeated_start(device_t dev, u_char slave, int timeout)
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{
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struct twsi_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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debugf(dev, "%s: slave=%x\n", __func__, slave);
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mtx_lock(&sc->mutex);
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rv = twsi_locked_start(dev, sc, TWSI_STATUS_RPTD_START, slave,
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timeout);
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mtx_unlock(&sc->mutex);
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if (rv) {
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twsi_stop(dev);
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return (rv);
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} else
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return (IIC_NOERR);
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}
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/*
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* timeout is given in us
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*/
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static int
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twsi_start(device_t dev, u_char slave, int timeout)
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{
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struct twsi_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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debugf(dev, "%s: slave=%x\n", __func__, slave);
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mtx_lock(&sc->mutex);
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rv = twsi_locked_start(dev, sc, TWSI_STATUS_START, slave, timeout);
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mtx_unlock(&sc->mutex);
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if (rv) {
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twsi_stop(dev);
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return (rv);
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} else
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return (IIC_NOERR);
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}
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static int
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twsi_read(device_t dev, char *buf, int len, int *read, int last, int delay)
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{
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struct twsi_softc *sc;
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uint32_t status;
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int last_byte, rv;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mutex);
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*read = 0;
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while (*read < len) {
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/*
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* Check if we are reading last byte of the last buffer,
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* do not send ACK then, per I2C specs
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*/
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last_byte = ((*read == len - 1) && last) ? 1 : 0;
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if (last_byte)
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twsi_control_clear(sc, TWSI_CONTROL_ACK);
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else
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twsi_control_set(sc, TWSI_CONTROL_ACK);
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twsi_clear_iflg(sc);
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DELAY(1000);
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if (twsi_poll_ctrl(sc, delay, TWSI_CONTROL_IFLG)) {
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debugf(dev, "timeout reading data (delay=%d)\n", delay);
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rv = IIC_ETIMEOUT;
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goto out;
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}
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status = TWSI_READ(sc, sc->reg_status);
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if (status != (last_byte ?
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TWSI_STATUS_DATA_RD_NOACK : TWSI_STATUS_DATA_RD_ACK)) {
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debugf(dev, "wrong status (%02x) while reading\n", status);
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rv = IIC_ESTATUS;
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goto out;
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}
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*buf++ = TWSI_READ(sc, sc->reg_data);
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(*read)++;
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}
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rv = IIC_NOERR;
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out:
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mtx_unlock(&sc->mutex);
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return (rv);
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}
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static int
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twsi_write(device_t dev, const char *buf, int len, int *sent, int timeout)
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{
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struct twsi_softc *sc;
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uint32_t status;
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int rv;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mutex);
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*sent = 0;
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while (*sent < len) {
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TWSI_WRITE(sc, sc->reg_data, *buf++);
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twsi_clear_iflg(sc);
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DELAY(1000);
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if (twsi_poll_ctrl(sc, timeout, TWSI_CONTROL_IFLG)) {
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debugf(dev, "timeout writing data (timeout=%d)\n", timeout);
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rv = IIC_ETIMEOUT;
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goto out;
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}
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status = TWSI_READ(sc, sc->reg_status);
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if (status != TWSI_STATUS_DATA_WR_ACK) {
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debugf(dev, "wrong status (%02x) while writing\n", status);
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rv = IIC_ESTATUS;
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goto out;
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}
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(*sent)++;
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}
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rv = IIC_NOERR;
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out:
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mtx_unlock(&sc->mutex);
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return (rv);
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}
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static int
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twsi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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struct twsi_softc *sc;
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sc = device_get_softc(dev);
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if (sc->have_intr == false)
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return (iicbus_transfer_gen(dev, msgs, nmsgs));
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sc->error = 0;
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sc->control_val = TWSI_CONTROL_TWSIEN |
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TWSI_CONTROL_INTEN | TWSI_CONTROL_ACK;
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TWSI_WRITE(sc, sc->reg_control, sc->control_val);
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debugf(dev, "transmitting %d messages\n", nmsgs);
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debugf(sc->dev, "status=%x\n", TWSI_READ(sc, sc->reg_status));
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sc->nmsgs = nmsgs;
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sc->msgs = msgs;
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sc->msg_idx = 0;
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sc->transfer = 1;
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/* Send start and re-enable interrupts */
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sc->control_val = TWSI_CONTROL_TWSIEN |
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TWSI_CONTROL_INTEN | TWSI_CONTROL_ACK;
|
|
if (sc->msgs[0].len == 1)
|
|
sc->control_val &= ~TWSI_CONTROL_ACK;
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val | TWSI_CONTROL_START);
|
|
while (sc->error == 0 && sc->transfer != 0) {
|
|
pause_sbt("twsi", SBT_1MS * 30, SBT_1MS, 0);
|
|
}
|
|
debugf(sc->dev, "pause finish\n");
|
|
|
|
if (sc->error) {
|
|
debugf(sc->dev, "Error, aborting (%d)\n", sc->error);
|
|
TWSI_WRITE(sc, sc->reg_control, 0);
|
|
}
|
|
|
|
/* Disable module and interrupts */
|
|
debugf(sc->dev, "status=%x\n", TWSI_READ(sc, sc->reg_status));
|
|
TWSI_WRITE(sc, sc->reg_control, 0);
|
|
debugf(sc->dev, "status=%x\n", TWSI_READ(sc, sc->reg_status));
|
|
|
|
return (sc->error);
|
|
}
|
|
|
|
static void
|
|
twsi_intr(void *arg)
|
|
{
|
|
struct twsi_softc *sc;
|
|
uint32_t status;
|
|
int transfer_done = 0;
|
|
|
|
sc = arg;
|
|
|
|
debugf(sc->dev, "Got interrupt Current msg=%x\n", sc->msg_idx);
|
|
|
|
status = TWSI_READ(sc, sc->reg_status);
|
|
debugf(sc->dev, "initial status=%x\n", status);
|
|
|
|
switch (status) {
|
|
case TWSI_STATUS_START:
|
|
case TWSI_STATUS_RPTD_START:
|
|
/* Transmit the address */
|
|
debugf(sc->dev, "Send the address\n");
|
|
|
|
if (sc->msgs[sc->msg_idx].flags & IIC_M_RD)
|
|
TWSI_WRITE(sc, sc->reg_data,
|
|
sc->msgs[sc->msg_idx].slave | LSB);
|
|
else
|
|
TWSI_WRITE(sc, sc->reg_data,
|
|
sc->msgs[sc->msg_idx].slave & ~LSB);
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val);
|
|
break;
|
|
|
|
case TWSI_STATUS_ADDR_W_ACK:
|
|
debugf(sc->dev, "Ack received after transmitting the address (write)\n");
|
|
/* Directly send the first byte */
|
|
sc->sent_bytes = 0;
|
|
debugf(sc->dev, "Sending byte 0 = %x\n", sc->msgs[sc->msg_idx].buf[0]);
|
|
TWSI_WRITE(sc, sc->reg_data, sc->msgs[sc->msg_idx].buf[0]);
|
|
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val);
|
|
break;
|
|
|
|
case TWSI_STATUS_ADDR_R_ACK:
|
|
debugf(sc->dev, "Ack received after transmitting the address (read)\n");
|
|
sc->recv_bytes = 0;
|
|
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val);
|
|
break;
|
|
|
|
case TWSI_STATUS_ADDR_W_NACK:
|
|
case TWSI_STATUS_ADDR_R_NACK:
|
|
debugf(sc->dev, "No ack received after transmitting the address\n");
|
|
sc->transfer = 0;
|
|
sc->error = ETIMEDOUT;
|
|
sc->control_val = 0;
|
|
wakeup(sc);
|
|
break;
|
|
|
|
case TWSI_STATUS_DATA_WR_ACK:
|
|
debugf(sc->dev, "Ack received after transmitting data\n");
|
|
if (sc->sent_bytes++ == (sc->msgs[sc->msg_idx].len - 1)) {
|
|
debugf(sc->dev, "Done sending all the bytes for msg %d\n", sc->msg_idx);
|
|
/* Send stop, no interrupts on stop */
|
|
if (!(sc->msgs[sc->msg_idx].flags & IIC_M_NOSTOP)) {
|
|
debugf(sc->dev, "Done TX data, send stop\n");
|
|
TWSI_WRITE(sc, sc->reg_control,
|
|
sc->control_val | TWSI_CONTROL_STOP);
|
|
} else {
|
|
debugf(sc->dev, "Done TX data with NO_STOP\n");
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val | TWSI_CONTROL_START);
|
|
}
|
|
sc->msg_idx++;
|
|
if (sc->msg_idx == sc->nmsgs) {
|
|
debugf(sc->dev, "transfer_done=1\n");
|
|
transfer_done = 1;
|
|
}
|
|
} else {
|
|
debugf(sc->dev, "Sending byte %d = %x\n",
|
|
sc->sent_bytes,
|
|
sc->msgs[sc->msg_idx].buf[sc->sent_bytes]);
|
|
TWSI_WRITE(sc, sc->reg_data,
|
|
sc->msgs[sc->msg_idx].buf[sc->sent_bytes]);
|
|
TWSI_WRITE(sc, sc->reg_control,
|
|
sc->control_val);
|
|
}
|
|
break;
|
|
|
|
case TWSI_STATUS_DATA_RD_ACK:
|
|
debugf(sc->dev, "Ack received after receiving data\n");
|
|
debugf(sc->dev, "msg_len=%d recv_bytes=%d\n", sc->msgs[sc->msg_idx].len, sc->recv_bytes);
|
|
sc->msgs[sc->msg_idx].buf[sc->recv_bytes++] = TWSI_READ(sc, sc->reg_data);
|
|
|
|
/* If we only have one byte left, disable ACK */
|
|
if (sc->msgs[sc->msg_idx].len - sc->recv_bytes == 1)
|
|
sc->control_val &= ~TWSI_CONTROL_ACK;
|
|
if (sc->msgs[sc->msg_idx].len - sc->recv_bytes) {
|
|
sc->msg_idx++;
|
|
if (sc->msg_idx == sc->nmsgs - 1)
|
|
transfer_done = 1;
|
|
}
|
|
TWSI_WRITE(sc, sc->reg_control, sc->control_val);
|
|
break;
|
|
|
|
case TWSI_STATUS_DATA_RD_NOACK:
|
|
if (sc->msgs[sc->msg_idx].len - sc->recv_bytes == 1) {
|
|
sc->msgs[sc->msg_idx].buf[sc->recv_bytes++] = TWSI_READ(sc, sc->reg_data);
|
|
debugf(sc->dev, "Done RX data, send stop (2)\n");
|
|
if (!(sc->msgs[sc->msg_idx].flags & IIC_M_NOSTOP))
|
|
TWSI_WRITE(sc, sc->reg_control,
|
|
sc->control_val | TWSI_CONTROL_STOP);
|
|
} else {
|
|
debugf(sc->dev, "No ack when receiving data\n");
|
|
sc->error = ENXIO;
|
|
sc->control_val = 0;
|
|
}
|
|
sc->transfer = 0;
|
|
transfer_done = 1;
|
|
break;
|
|
|
|
default:
|
|
debugf(sc->dev, "status=%x hot handled\n", status);
|
|
sc->transfer = 0;
|
|
sc->error = ENXIO;
|
|
sc->control_val = 0;
|
|
wakeup(sc);
|
|
break;
|
|
}
|
|
|
|
debugf(sc->dev, "Done with interrupts\n\n");
|
|
if (transfer_done == 1) {
|
|
sc->transfer = 0;
|
|
wakeup(sc);
|
|
}
|
|
}
|
|
|
|
static void
|
|
twsi_intr_start(void *pdev)
|
|
{
|
|
struct twsi_softc *sc;
|
|
|
|
sc = device_get_softc(pdev);
|
|
|
|
if ((bus_setup_intr(pdev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, twsi_intr, sc, &sc->intrhand)))
|
|
device_printf(pdev, "unable to register interrupt handler\n");
|
|
|
|
sc->have_intr = true;
|
|
}
|
|
|
|
int
|
|
twsi_attach(device_t dev)
|
|
{
|
|
struct twsi_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
mtx_init(&sc->mutex, device_get_nameunit(dev), "twsi", MTX_DEF);
|
|
|
|
if (bus_alloc_resources(dev, res_spec, sc->res)) {
|
|
device_printf(dev, "could not allocate resources\n");
|
|
twsi_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Attach the iicbus. */
|
|
if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
|
|
device_printf(dev, "could not allocate iicbus instance\n");
|
|
twsi_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
bus_generic_attach(dev);
|
|
|
|
config_intrhook_oneshot(twsi_intr_start, dev);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
twsi_detach(device_t dev)
|
|
{
|
|
struct twsi_softc *sc;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if ((rv = bus_generic_detach(dev)) != 0)
|
|
return (rv);
|
|
|
|
if (sc->iicbus != NULL)
|
|
if ((rv = device_delete_child(dev, sc->iicbus)) != 0)
|
|
return (rv);
|
|
|
|
if (sc->intrhand != NULL)
|
|
bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
|
|
|
|
bus_release_resources(dev, res_spec, sc->res);
|
|
|
|
mtx_destroy(&sc->mutex);
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t twsi_methods[] = {
|
|
/* device interface */
|
|
DEVMETHOD(device_detach, twsi_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
|
|
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
|
|
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
|
|
|
|
/* iicbus interface */
|
|
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
|
DEVMETHOD(iicbus_repeated_start, twsi_repeated_start),
|
|
DEVMETHOD(iicbus_start, twsi_start),
|
|
DEVMETHOD(iicbus_stop, twsi_stop),
|
|
DEVMETHOD(iicbus_write, twsi_write),
|
|
DEVMETHOD(iicbus_read, twsi_read),
|
|
DEVMETHOD(iicbus_reset, twsi_reset),
|
|
DEVMETHOD(iicbus_transfer, twsi_transfer),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
DEFINE_CLASS_0(twsi, twsi_driver, twsi_methods,
|
|
sizeof(struct twsi_softc));
|