159 lines
4.3 KiB
C
159 lines
4.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* $FreeBSD$
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*
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*/
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#ifndef _PCI_DW_H_
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#define _PCI_DW_H_
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#include "pci_dw_if.h"
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/* DesignWare CIe configuration registers */
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#define DW_PORT_LINK_CTRL 0x710
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#define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)
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#define PORT_LINK_CAPABLE_1 0x01
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#define PORT_LINK_CAPABLE_2 0x03
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#define PORT_LINK_CAPABLE_4 0x07
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#define PORT_LINK_CAPABLE_8 0x0F
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#define PORT_LINK_CAPABLE_16 0x1F
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#define PORT_LINK_CAPABLE_32 0x3F
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#define DW_GEN2_CTRL 0x80C
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#define DIRECT_SPEED_CHANGE (1 << 17)
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#define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)
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#define GEN2_CTRL_NUM_OF_LANES_1 0x01
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#define GEN2_CTRL_NUM_OF_LANES_2 0x03
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#define GEN2_CTRL_NUM_OF_LANES_4 0x07
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#define GEN2_CTRL_NUM_OF_LANES_8 0x0F
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#define GEN2_CTRL_NUM_OF_LANES_16 0x1F
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#define GEN2_CTRL_NUM_OF_LANES_32 0x3F
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#define DW_MSI_ADDR_LO 0x820
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#define DW_MSI_ADDR_HI 0x824
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#define DW_MSI_INTR0_ENABLE 0x828
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#define DW_MSI_INTR0_MASK 0x82C
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#define DW_MSI_INTR0_STATUS 0x830
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#define DW_MISC_CONTROL_1 0x8BC
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#define DBI_RO_WR_EN (1 << 0)
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#define DW_IATU_VIEWPORT 0x900
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#define IATU_REGION_INBOUND (1U << 31)
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#define IATU_REGION_INDEX(x) ((x) & 0x7)
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#define DW_IATU_CTRL1 0x904
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#define IATU_CTRL1_TYPE(x) ((x) & 0x1F)
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#define IATU_CTRL1_TYPE_MEM 0x0
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#define IATU_CTRL1_TYPE_IO 0x2
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#define IATU_CTRL1_TYPE_CFG0 0x4
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#define IATU_CTRL1_TYPE_CFG1 0x5
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#define DW_IATU_CTRL2 0x908
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#define IATU_CTRL2_REGION_EN (1U << 31)
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#define DW_IATU_LWR_BASE_ADDR 0x90C
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#define DW_IATU_UPPER_BASE_ADDR 0x910
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#define DW_IATU_LIMIT_ADDR 0x914
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#define DW_IATU_LWR_TARGET_ADDR 0x918
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#define DW_IATU_UPPER_TARGET_ADDR 0x91C
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struct pci_dw_softc {
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struct ofw_pci_softc ofw_pci; /* Must be first */
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/* Filled by attachement stub */
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struct resource *dbi_res;
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/* pci_dw variables */
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device_t dev;
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phandle_t node;
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struct mtx mtx;
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struct resource *cfg_res;
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struct ofw_pci_range mem_range;
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struct ofw_pci_range pref_mem_range;
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struct ofw_pci_range io_range;
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bool coherent;
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bus_dma_tag_t dmat;
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int num_lanes;
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int num_viewport;
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bus_addr_t cfg_pa; /* PA of config memoty */
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bus_size_t cfg_size; /* size of config region */
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u_int bus_start;
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u_int bus_end;
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u_int root_bus;
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u_int sub_bus;
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};
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DECLARE_CLASS(pci_dw_driver);
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static inline void
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pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val)
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{
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PCI_DW_DBI_WRITE(dev, reg, val, 4);
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}
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static inline void
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pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val)
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{
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PCI_DW_DBI_WRITE(dev, reg, val, 2);
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}
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static inline void
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pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val)
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{
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PCI_DW_DBI_WRITE(dev, reg, val, 1);
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}
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static inline uint32_t
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pci_dw_dbi_rd4(device_t dev, u_int reg)
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{
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return (PCI_DW_DBI_READ(dev, reg, 4));
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}
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static inline uint16_t
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pci_dw_dbi_rd2(device_t dev, u_int reg)
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{
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return ((uint16_t)PCI_DW_DBI_READ(dev, reg, 2));
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}
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static inline uint8_t
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pci_dw_dbi_rd1(device_t dev, u_int reg)
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{
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return ((uint8_t)PCI_DW_DBI_READ(dev, reg, 1));
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}
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int pci_dw_init(device_t);
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#endif /* __PCI_HOST_GENERIC_H_ */
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