8c1093fc50
take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/*-
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* Copyright (c) 2008 Nathan Whitehorn
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* Copyright (c) 2003 Peter Grehan
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Number of transmit/receive DBDMA descriptors.
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* XXX allow override with a tuneable ?
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*/
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#define BM_MAX_DMA_COMMANDS 256
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#define BM_NTXSEGS 16
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#define BM_MAX_TX_PACKETS 100
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#define BM_MAX_RX_PACKETS 100
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/*
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* Mutex macros
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*/
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#define BM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define BM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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/*
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* software state for transmit job mbufs (may be elements of mbuf chains)
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*/
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struct bm_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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int txs_firstdesc; /* first descriptor in packet */
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int txs_lastdesc; /* last descriptor in packet */
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int txs_stopdesc; /* the location of the closing STOP */
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int txs_ndescs; /* number of descriptors */
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STAILQ_ENTRY(bm_txsoft) txs_q;
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};
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STAILQ_HEAD(bm_txsq, bm_txsoft);
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/*
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* software state for receive jobs
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*/
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struct bm_rxsoft {
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struct mbuf *rxs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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int dbdma_slot;
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bus_dma_segment_t segment;
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};
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struct bm_softc {
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struct ifnet *sc_ifp;
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struct mtx sc_mtx;
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u_char sc_enaddr[ETHER_ADDR_LEN];
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int sc_streaming;
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int sc_ifpflags;
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int sc_duplex;
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int sc_wdog_timer;
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struct callout sc_tick_ch;
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device_t sc_dev; /* back ptr to dev */
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struct resource *sc_memr; /* macio bus mem resource */
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int sc_memrid;
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device_t sc_miibus;
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struct mii_data *sc_mii;
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struct resource *sc_txdmar, *sc_rxdmar;
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int sc_txdmarid, sc_rxdmarid;
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struct resource *sc_txdmairq, *sc_rxdmairq;
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void *sc_txihtx, *sc_rxih;
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int sc_txdmairqid, sc_rxdmairqid;
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bus_dma_tag_t sc_pdma_tag;
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bus_dma_tag_t sc_tdma_tag;
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struct bm_txsoft sc_txsoft[BM_MAX_TX_PACKETS];
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int first_used_txdma_slot, next_txdma_slot;
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struct bm_txsq sc_txfreeq;
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struct bm_txsq sc_txdirtyq;
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bus_dma_tag_t sc_rdma_tag;
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struct bm_rxsoft sc_rxsoft[BM_MAX_TX_PACKETS];
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int next_rxdma_slot, rxdma_loop_slot;
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dbdma_channel_t *sc_txdma, *sc_rxdma;
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};
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