Jung-uk Kim 3453537fa5 Use atomic load & store for TSC frequency. It may be overkill for amd64 but ... safer for i386 because it can be easily over 4 GHz now. More worse, it can be easily changed by user with 'machdep.tsc_freq' tunable (directly) or cpufreq(4) (indirectly). Note it is intentionally not used in performance critical paths to avoid performance regression (but we should, in theory). Alternatively, we may add "virtual TSC" with lower frequency if maximum frequency overflows 32 bits (and ignore possible incoherency as we do now).		2011-04-07 23:28:28 +00:00
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amd64	Use atomic load & store for TSC frequency. It may be overkill for amd64 but	2011-04-07 23:28:28 +00:00
i386	Use atomic load & store for TSC frequency. It may be overkill for amd64 but	2011-04-07 23:28:28 +00:00
dtrace_anon.c
dtrace_cddl.h	Add more compatibility structure members needed by the upcoming fasttrap	2010-08-22 11:04:43 +00:00
dtrace_clone.c
dtrace_debug.c	Update several places that iterate over CPUs to use CPU_FOREACH().	2010-06-11 18:46:34 +00:00
dtrace_hacks.c
dtrace_ioctl.c	Kernel DTrace support for:	2010-08-22 10:53:32 +00:00
dtrace_load.c	Make the /dev/dtrace/helper node have the mode 0660. This allows	2010-09-01 12:08:32 +00:00
dtrace_modevent.c
dtrace_sysctl.c
dtrace_test.c
dtrace_unload.c	Destroy the helper device when unloading.	2010-08-22 11:05:37 +00:00
dtrace_vtime.c