718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
526 lines
12 KiB
C
526 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006 Juniper Networks
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <dev/ic/quicc.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK ((266000000 * 2) / 16)
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#define quicc_read2(bas, reg) \
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bus_space_read_2((bas)->bst, (bas)->bsh, reg)
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#define quicc_read4(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, reg)
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#define quicc_write2(bas, reg, val) \
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bus_space_write_2((bas)->bst, (bas)->bsh, reg, val)
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#define quicc_write4(bas, reg, val) \
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bus_space_write_4((bas)->bst, (bas)->bsh, reg, val)
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static int
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quicc_divisor(int rclk, int baudrate)
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{
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int act_baud, divisor, error;
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if (baudrate == 0)
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return (-1);
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divisor = rclk / baudrate / 16;
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if (divisor > 4096)
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divisor = ((divisor >> 3) - 2) | 1;
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else if (divisor >= 0)
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divisor = (divisor - 1) << 1;
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if (divisor < 0 || divisor >= 8192)
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return (-1);
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act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4));
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/* 10 times error in percent: */
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error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
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/* 3.0% maximum error tolerance: */
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if (error < -30 || error > 30)
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return (-1);
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return (divisor);
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}
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static int
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quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int divisor;
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uint16_t psmr;
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if (baudrate > 0) {
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divisor = quicc_divisor(bas->rclk, baudrate);
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if (divisor == -1)
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return (EINVAL);
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quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1),
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divisor | 0x10000);
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}
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psmr = 0;
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switch (databits) {
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case 5: psmr |= 0x0000; break;
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case 6: psmr |= 0x1000; break;
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case 7: psmr |= 0x2000; break;
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case 8: psmr |= 0x3000; break;
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default: return (EINVAL);
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}
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switch (stopbits) {
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case 1: psmr |= 0x0000; break;
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case 2: psmr |= 0x4000; break;
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default: return (EINVAL);
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}
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switch (parity) {
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case UART_PARITY_EVEN: psmr |= 0x1a; break;
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case UART_PARITY_MARK: psmr |= 0x1f; break;
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case UART_PARITY_NONE: psmr |= 0x00; break;
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case UART_PARITY_ODD: psmr |= 0x10; break;
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case UART_PARITY_SPACE: psmr |= 0x15; break;
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default: return (EINVAL);
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}
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quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr);
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return (0);
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}
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static void
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quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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/*
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* GSMR_L = 0x00028034
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* GSMR_H = 0x00000020
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*/
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quicc_param(bas, baudrate, databits, stopbits, parity);
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quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
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quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);
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}
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/*
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* Low-level UART interface.
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*/
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static int quicc_probe(struct uart_bas *bas);
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static void quicc_init(struct uart_bas *bas, int, int, int, int);
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static void quicc_term(struct uart_bas *bas);
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static void quicc_putc(struct uart_bas *bas, int);
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static int quicc_rxready(struct uart_bas *bas);
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static int quicc_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_quicc_ops = {
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.probe = quicc_probe,
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.init = quicc_init,
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.term = quicc_term,
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.putc = quicc_putc,
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.rxready = quicc_rxready,
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.getc = quicc_getc,
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};
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static int
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quicc_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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quicc_setup(bas, baudrate, databits, stopbits, parity);
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}
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static void
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quicc_term(struct uart_bas *bas)
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{
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}
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static void
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quicc_putc(struct uart_bas *bas, int c)
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{
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int unit;
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uint16_t toseq;
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unit = bas->chan - 1;
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while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)
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DELAY(10);
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toseq = 0x2000 | (c & 0xff);
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quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq);
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}
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static int
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quicc_rxready(struct uart_bas *bas)
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{
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uint16_t rb;
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rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
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return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);
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}
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static int
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quicc_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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volatile char *buf;
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int c;
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uint16_t rb, sc;
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uart_lock(hwmtx);
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rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
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while ((sc = quicc_read2(bas, rb)) & 0x8000) {
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uart_unlock(hwmtx);
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DELAY(4);
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uart_lock(hwmtx);
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}
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buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
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c = *buf;
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quicc_write2(bas, rb, sc | 0x8000);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct quicc_softc {
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struct uart_softc base;
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};
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static int quicc_bus_attach(struct uart_softc *);
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static int quicc_bus_detach(struct uart_softc *);
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static int quicc_bus_flush(struct uart_softc *, int);
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static int quicc_bus_getsig(struct uart_softc *);
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static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int quicc_bus_ipend(struct uart_softc *);
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static int quicc_bus_param(struct uart_softc *, int, int, int, int);
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static int quicc_bus_probe(struct uart_softc *);
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static int quicc_bus_receive(struct uart_softc *);
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static int quicc_bus_setsig(struct uart_softc *, int);
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static int quicc_bus_transmit(struct uart_softc *);
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static void quicc_bus_grab(struct uart_softc *);
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static void quicc_bus_ungrab(struct uart_softc *);
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static kobj_method_t quicc_methods[] = {
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KOBJMETHOD(uart_attach, quicc_bus_attach),
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KOBJMETHOD(uart_detach, quicc_bus_detach),
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KOBJMETHOD(uart_flush, quicc_bus_flush),
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KOBJMETHOD(uart_getsig, quicc_bus_getsig),
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KOBJMETHOD(uart_ioctl, quicc_bus_ioctl),
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KOBJMETHOD(uart_ipend, quicc_bus_ipend),
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KOBJMETHOD(uart_param, quicc_bus_param),
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KOBJMETHOD(uart_probe, quicc_bus_probe),
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KOBJMETHOD(uart_receive, quicc_bus_receive),
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KOBJMETHOD(uart_setsig, quicc_bus_setsig),
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KOBJMETHOD(uart_transmit, quicc_bus_transmit),
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KOBJMETHOD(uart_grab, quicc_bus_grab),
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KOBJMETHOD(uart_ungrab, quicc_bus_ungrab),
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{ 0, 0 }
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};
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struct uart_class uart_quicc_class = {
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"quicc",
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quicc_methods,
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sizeof(struct quicc_softc),
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.uc_ops = &uart_quicc_ops,
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.uc_range = 2,
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.uc_rclk = DEFAULT_RCLK,
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.uc_rshift = 0
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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quicc_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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struct uart_devinfo *di;
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uint16_t st, rb;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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quicc_param(bas, di->baudrate, di->databits, di->stopbits,
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di->parity);
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} else {
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quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE);
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}
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/* Enable interrupts on the receive buffer. */
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rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
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st = quicc_read2(bas, rb);
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quicc_write2(bas, rb, st | 0x9000);
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(void)quicc_bus_getsig(sc);
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return (0);
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}
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static int
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quicc_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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quicc_bus_flush(struct uart_softc *sc, int what)
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{
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return (0);
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}
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static int
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quicc_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint32_t dummy;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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/* XXX SIGNALS */
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dummy = 0;
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uart_unlock(sc->sc_hwmtx);
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SIGCHG(dummy, sig, SER_CTS, SER_DCTS);
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SIGCHG(dummy, sig, SER_DCD, SER_DDCD);
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SIGCHG(dummy, sig, SER_DSR, SER_DDSR);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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uint32_t brg;
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int baudrate, error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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break;
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case UART_IOCTL_BAUD:
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brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;
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brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1;
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baudrate = bas->rclk / (brg * 16);
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*(int*)data = baudrate;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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quicc_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint16_t scce;
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1));
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quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);
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uart_unlock(sc->sc_hwmtx);
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if (scce & 0x0001)
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ipend |= SER_INT_RXREADY;
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if (scce & 0x0002)
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ipend |= SER_INT_TXIDLE;
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if (scce & 0x0004)
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ipend |= SER_INT_OVERRUN;
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if (scce & 0x0020)
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ipend |= SER_INT_BREAK;
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/* XXX SIGNALS */
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return (ipend);
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}
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static int
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quicc_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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int error;
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uart_lock(sc->sc_hwmtx);
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error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits,
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parity);
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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quicc_bus_probe(struct uart_softc *sc)
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{
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char buf[80];
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int error;
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error = quicc_probe(&sc->sc_bas);
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if (error)
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return (error);
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sc->sc_rxfifosz = 1;
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sc->sc_txfifosz = 1;
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snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan);
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device_set_desc_copy(sc->sc_dev, buf);
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return (0);
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}
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static int
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quicc_bus_receive(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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volatile char *buf;
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uint16_t st, rb;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
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st = quicc_read2(bas, rb);
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buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4);
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uart_rx_put(sc, *buf);
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quicc_write2(bas, rb, st | 0x9000);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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quicc_bus_setsig(struct uart_softc *sc, int sig)
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{
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struct uart_bas *bas;
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uint32_t new, old;
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bas = &sc->sc_bas;
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do {
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old = sc->sc_hwsig;
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new = old;
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if (sig & SER_DDTR) {
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SIGCHG(sig & SER_DTR, new, SER_DTR,
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SER_DDTR);
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}
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if (sig & SER_DRTS) {
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SIGCHG(sig & SER_RTS, new, SER_RTS,
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SER_DRTS);
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}
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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uart_lock(sc->sc_hwmtx);
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/* XXX SIGNALS */
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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quicc_bus_transmit(struct uart_softc *sc)
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{
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volatile char *buf;
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struct uart_bas *bas;
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uint16_t st, tb;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1));
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st = quicc_read2(bas, tb);
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buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4);
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*buf = sc->sc_txbuf[0];
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quicc_write2(bas, tb + 2, 1);
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quicc_write2(bas, tb, st | 0x9000);
|
|
sc->sc_txbusy = 1;
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
quicc_bus_grab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
uint16_t st, rb;
|
|
|
|
/* Disable interrupts on the receive buffer. */
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
|
|
st = quicc_read2(bas, rb);
|
|
quicc_write2(bas, rb, st & ~0x9000);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|
|
static void
|
|
quicc_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas;
|
|
uint16_t st, rb;
|
|
|
|
/* Enable interrupts on the receive buffer. */
|
|
bas = &sc->sc_bas;
|
|
uart_lock(sc->sc_hwmtx);
|
|
rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1));
|
|
st = quicc_read2(bas, rb);
|
|
quicc_write2(bas, rb, st | 0x9000);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
}
|
|
|