263 lines
7.0 KiB
Markdown
263 lines
7.0 KiB
Markdown
;; Scheduling description for z990 (cpu 2084).
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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;; Ulrich Weigand (uweigand@de.ibm.com).
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify it under
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;; the terms of the GNU General Public License as published by the Free
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;; Software Foundation; either version 2, or (at your option) any later
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;; version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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;; for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to the Free
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;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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;; 02111-1307, USA.
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(define_automaton "x_ipu")
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(define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu")
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(define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
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(define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu")
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(define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu")
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(define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu")
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(define_cpu_unit "x_store_tok" "x_ipu")
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(define_cpu_unit "x_ms,x_mt" "x_ipu")
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(define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
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(define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
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(absence_set "x_e1_r" "x_e1_s,x_e1_t")
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(absence_set "x_e1_s" "x_e1_t")
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;; Try to avoid int <-> fp transitions.
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(define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
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(define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
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(define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
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(define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
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(define_reservation "x-wr-fp" "x_wr_fp,x-f")
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(define_reservation "x-mem" "x_ms|x_mt")
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(absence_set "x_wr_fp"
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"x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
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(absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
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"x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
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;; Don't have any load type insn in same group as store
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(absence_set "x_ms,x_mt" "x_store_tok")
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;;
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;; Simple insns
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;;
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(define_insn_reservation "x_lr" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "lr"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_la" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "la"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_larl" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "larl"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_load" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "load"))
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"x-e1-st+x-mem,x-wr-st")
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(define_insn_reservation "x_store" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "store"))
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"x-e1-st+x_store_tok,x-wr-st")
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(define_insn_reservation "x_branch" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "branch"))
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"x_e1_r,x_wr_r")
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(define_insn_reservation "x_call" 5
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "jsr"))
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"x-e1-np*5,x-wr-np")
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;;
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;; Multicycle insns
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;;
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(define_insn_reservation "x_ss" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "op_type" "SS"))
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"x-e1-np,x-wr-np")
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(define_insn_reservation "x_stm" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "stm"))
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"(x-e1-np+x_store_tok)*10,x-wr-np")
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(define_insn_reservation "x_lm" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "lm"))
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"x-e1-np*10,x-wr-np")
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(define_insn_reservation "x_nn" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "op_type" "NN"))
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"x-e1-np,x-wr-np")
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(define_insn_reservation "x_o2" 2
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o2"))
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"x-e1-np*2,x-wr-np")
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(define_insn_reservation "x_o3" 3
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o3"))
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"x-e1-np*3,x-wr-np")
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;;
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;; Floating point insns
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;;
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(define_insn_reservation "x_fsimpd" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fsimpd,fmuld"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fsimps" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fsimps,fmuls"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fdivd" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivd"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_fdivs" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivs"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_floadd" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "floadd"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_floads" 6
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "floads"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fstored" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fstored"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_fstores" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fstores"))
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"x_e1_t,x-wr-fp")
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(define_insn_reservation "x_ftoi" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "ftoi"))
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"x_e1_t*3,x-wr-fp")
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(define_insn_reservation "x_itof" 7
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "itof"))
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"x_e1_t*3,x-wr-fp")
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(define_bypass 1 "x_fsimpd" "x_fstored")
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(define_bypass 1 "x_fsimps" "x_fstores")
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(define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
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(define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
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;;
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;; Insns still not mentioned are checked for
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;; the usage of the agen unit
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;;
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(define_insn_reservation "x_int" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "atype" "reg"))
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"x-e1-st,x-wr-st")
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(define_insn_reservation "x_agen" 1
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(and (eq_attr "cpu" "z990")
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(eq_attr "atype" "agen"))
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"x-e1-st+x-mem,x-wr-st")
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;;
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;; s390_agen_dep_p returns 1, if a register is set in the
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;; first insn and used in the dependent insn to form a address.
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;;
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;;
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;; If an instruction uses a register to address memory, it needs
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;; to be set 5 cycles in advance.
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;;
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(define_bypass 5 "x_int,x_agen,x_lr"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 9 "x_int,x_agen,x_lr"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; A load type instruction uses a bypass to feed the result back
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;; to the address generation pipeline stage.
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;;
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(define_bypass 4 "x_load"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 5 "x_load"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; A load address type instruction uses a bypass to feed the
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;; result back to the address generation pipeline stage.
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;;
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(define_bypass 3 "x_larl,x_la"
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"x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
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"s390_agen_dep_p")
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(define_bypass 5 "x_larl, x_la"
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"x_floadd, x_floads, x_fstored, x_fstores,\
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x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
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"s390_agen_dep_p")
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;;
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;; Operand forwarding
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;;
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(define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
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