37507c1bd2
operands that are set during seqeuncer program download instead of at assembly time. Convert the sequencer code to use" downloaded constants" for four run time constants that vary depending on the board type. This frees up 4 bytes of sequencer scratch ram space where these constants used to be stored and also removes the additional instructions required to load their values into the accumulator prior to using them. Remove the REJBYTE sram variable. The host driver can just as easly read the accumulator to get this value. The scratch ram savings is important as the old code used to clober the SCSICONF register on 274X cards which sits near the top of scratch ram space. The SCSICONF register controls bus termination, and clobbering it is not a good thing. Now we have 4 bytes to spare. This should fix the reported problems with cards that don't have devices attached to them failing with a stream of "Somone reset bus X" messages. Doug Ledford determined the cause of the problem, fixes by me.
98 lines
3.2 KiB
C
98 lines
3.2 KiB
C
/*
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* Instruction formats for the sequencer program downloaded to
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* Aic7xxx SCSI host adapters
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*
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* Copyright (c) 1997 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Where this Software is combined with software released under the terms of
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* the GNU Public License ("GPL") and the terms of the GPL would require the
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* combined work to also be released under the terms of the GPL, the terms
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* and conditions of this License will apply in addition to those of the
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* GPL with the exception of any terms or conditions of this License that
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* conflict with, or are expressly prohibited by, the GPL.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: sequencer.h,v 1.2 1997/06/27 19:38:52 gibbs Exp $
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*/
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struct ins_format1 {
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u_int8_t immediate;
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u_int8_t source;
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u_int8_t destination;
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u_int8_t opcode_ret;
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#define DOWNLOAD_CONST_IMMEDIATE 0x80
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};
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struct ins_format2 {
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u_int8_t shift_control;
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u_int8_t source;
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u_int8_t destination;
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u_int8_t opcode_ret;
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#define RETURN_BIT 0x01
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};
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struct ins_format3 {
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u_int8_t immediate;
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u_int8_t source;
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u_int8_t address;
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u_int8_t opcode_addr;
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#define ADDR_HIGH_BIT 0x01
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};
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struct instruction {
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union {
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struct ins_format1 format1;
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struct ins_format2 format2;
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struct ins_format3 format3;
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u_int8_t bytes[4];
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} format;
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u_int srcline;
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struct symbol *patch_label;
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STAILQ_ENTRY(instruction) links;
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};
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#define AIC_OP_OR 0x0
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#define AIC_OP_AND 0x1
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#define AIC_OP_XOR 0x2
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#define AIC_OP_ADD 0x3
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#define AIC_OP_ADC 0x4
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#define AIC_OP_ROL 0x5
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#define AIC_OP_JMP 0x8
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#define AIC_OP_JC 0x9
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#define AIC_OP_JNC 0xa
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#define AIC_OP_CALL 0xb
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#define AIC_OP_JNE 0xc
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#define AIC_OP_JNZ 0xd
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#define AIC_OP_JE 0xe
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#define AIC_OP_JZ 0xf
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/* Pseudo Ops */
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#define AIC_OP_SHL 0x10
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#define AIC_OP_SHR 0x20
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#define AIC_OP_ROR 0x30
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