135 lines
4.8 KiB
C++
135 lines
4.8 KiB
C++
//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUSubtarget.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "R600MachineScheduler.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-subtarget"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "AMDGPUGenSubtargetInfo.inc"
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AMDGPUSubtarget &
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AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU,
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StringRef FS) {
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// Determine default and user-specified characteristics
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// On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
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// enabled, but some instructions do not respect them and they run at the
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// double precision rate, so don't enable by default.
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//
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// We want to be able to turn these off, but making this a subtarget feature
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// for SI has the unhelpful behavior that it unsets everything else if you
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// disable it.
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SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
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FullFS += FS;
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if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn)
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GPU = "SI";
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ParseSubtargetFeatures(GPU, FullFS);
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// FIXME: I don't think think Evergreen has any useful support for
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// denormals, but should be checked. Should we issue a warning somewhere
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// if someone tries to enable these?
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if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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FP32Denormals = false;
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FP64Denormals = false;
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}
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return *this;
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}
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AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
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TargetMachine &TM)
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: AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
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DumpCode(false), R600ALUInst(false), HasVertexCache(false),
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TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
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CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
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EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
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WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
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EnableVGPRSpilling(false), SGPRInitBug(false),
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IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false),
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LDSBankCount(0),
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FrameLowering(TargetFrameLowering::StackGrowsUp,
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64 * 16, // Maximum stack alignment (long16)
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0),
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InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
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initializeSubtargetDependencies(TT, GPU, FS);
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if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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InstrInfo.reset(new R600InstrInfo(*this));
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TLInfo.reset(new R600TargetLowering(TM, *this));
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} else {
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InstrInfo.reset(new SIInstrInfo(*this));
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TLInfo.reset(new SITargetLowering(TM, *this));
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}
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}
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unsigned AMDGPUSubtarget::getStackEntrySize() const {
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assert(getGeneration() <= NORTHERN_ISLANDS);
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switch(getWavefrontSize()) {
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case 16:
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return 8;
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case 32:
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return hasCaymanISA() ? 4 : 8;
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case 64:
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return 4;
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default:
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llvm_unreachable("Illegal wavefront size.");
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}
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}
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unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
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switch(getGeneration()) {
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default: llvm_unreachable("ChipID unknown");
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case SEA_ISLANDS: return 12;
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}
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}
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bool AMDGPUSubtarget::isVGPRSpillingEnabled(
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const SIMachineFunctionInfo *MFI) const {
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return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
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}
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void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin,
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MachineInstr *end,
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unsigned NumRegionInstrs) const {
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if (getGeneration() >= SOUTHERN_ISLANDS) {
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// Track register pressure so the scheduler can try to decrease
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// pressure once register usage is above the threshold defined by
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// SIRegisterInfo::getRegPressureSetLimit()
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Policy.ShouldTrackPressure = true;
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// Enabling both top down and bottom up scheduling seems to give us less
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// register spills than just using one of these approaches on its own.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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}
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}
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