92 lines
2.7 KiB
TableGen
92 lines
2.7 KiB
TableGen
//===-- SISchedule.td - SI Scheduling definitons -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineModel definitions for Southern Islands (SI)
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//
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//===----------------------------------------------------------------------===//
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def WriteBranch : SchedWrite;
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def WriteExport : SchedWrite;
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def WriteLDS : SchedWrite;
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def WriteSALU : SchedWrite;
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def WriteSMEM : SchedWrite;
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def WriteVMEM : SchedWrite;
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// Vector ALU instructions
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def Write32Bit : SchedWrite;
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def WriteQuarterRate32 : SchedWrite;
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def WriteFloatFMA : SchedWrite;
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def WriteDouble : SchedWrite;
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def WriteDoubleAdd : SchedWrite;
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def SIFullSpeedModel : SchedMachineModel;
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def SIQuarterSpeedModel : SchedMachineModel;
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// BufferSize = 0 means the processors are in-order.
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let BufferSize = 0 in {
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// XXX: Are the resource counts correct?
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def HWBranch : ProcResource<1>;
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def HWExport : ProcResource<7>; // Taken from S_WAITCNT
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def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
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def HWSALU : ProcResource<1>;
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def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT
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def HWVALU : ProcResource<1>;
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}
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class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
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int latency> : WriteRes<write, resources> {
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let Latency = latency;
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}
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class HWVALUWriteRes<SchedWrite write, int latency> :
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HWWriteRes<write, [HWVALU], latency>;
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// The latency numbers are taken from AMD Accelerated Parallel Processing
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// guide. They may not be acurate.
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// The latency values are 1 / (operations / cycle) / 4.
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multiclass SICommonWriteRes {
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def : HWWriteRes<WriteBranch, [HWBranch], 100>; // XXX: Guessed ???
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def : HWWriteRes<WriteExport, [HWExport], 100>; // XXX: Guessed ???
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def : HWWriteRes<WriteLDS, [HWLGKM], 32>; // 2 - 64
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def : HWWriteRes<WriteSALU, [HWSALU], 1>;
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def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ???
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def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600
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def : HWVALUWriteRes<Write32Bit, 1>;
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def : HWVALUWriteRes<WriteQuarterRate32, 4>;
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}
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let SchedModel = SIFullSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 1>;
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def : HWVALUWriteRes<WriteDouble, 4>;
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def : HWVALUWriteRes<WriteDoubleAdd, 2>;
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} // End SchedModel = SIFullSpeedModel
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let SchedModel = SIQuarterSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 16>;
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def : HWVALUWriteRes<WriteDouble, 16>;
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def : HWVALUWriteRes<WriteDoubleAdd, 8>;
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} // End SchedModel = SIQuarterSpeedModel
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