167 lines
6.1 KiB
C
167 lines
6.1 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2005-2006 Atheros Communications, Inc.
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* All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef __AH_REGDOMAIN_H__
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#define __AH_REGDOMAIN_H__
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/*
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* BMLEN defines the size of the bitmask used to hold frequency
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* band specifications. Note this must agree with the BM macro
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* definition that's used to setup initializers. See also further
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* comments below.
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*/
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#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */
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typedef uint64_t chanbmask_t[BMLEN];
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/*
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* The following describe the bit masks for different passive scan
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* capability/requirements per regdomain.
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*/
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#define NO_PSCAN 0x0ULL /* NB: must be zero */
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#define PSCAN_FCC 0x0000000000000001ULL
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#define PSCAN_FCC_T 0x0000000000000002ULL
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#define PSCAN_ETSI 0x0000000000000004ULL
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#define PSCAN_MKK1 0x0000000000000008ULL
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#define PSCAN_MKK2 0x0000000000000010ULL
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#define PSCAN_MKKA 0x0000000000000020ULL
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#define PSCAN_MKKA_G 0x0000000000000040ULL
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#define PSCAN_ETSIA 0x0000000000000080ULL
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#define PSCAN_ETSIB 0x0000000000000100ULL
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#define PSCAN_ETSIC 0x0000000000000200ULL
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#define PSCAN_WWR 0x0000000000000400ULL
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#define PSCAN_MKKA1 0x0000000000000800ULL
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#define PSCAN_MKKA1_G 0x0000000000001000ULL
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#define PSCAN_MKKA2 0x0000000000002000ULL
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#define PSCAN_MKKA2_G 0x0000000000004000ULL
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#define PSCAN_MKK3 0x0000000000008000ULL
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#define PSCAN_DEFER 0x7FFFFFFFFFFFFFFFULL
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#define IS_ECM_CHAN 0x8000000000000000ULL
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/*
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* The following are flags for different requirements per reg domain.
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* These requirements are either inhereted from the reg domain pair or
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* from the unitary reg domain if the reg domain pair flags value is 0
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*/
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enum {
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NO_REQ = 0x00000000, /* NB: must be zero */
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DISALLOW_ADHOC_11A = 0x00000001, /* adhoc not allowed in 5GHz */
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DISALLOW_ADHOC_11A_TURB = 0x00000002, /* not allowed w/ 5GHz turbo */
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NEED_NFC = 0x00000004, /* need noise floor check */
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ADHOC_PER_11D = 0x00000008, /* must receive 11d beacon */
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LIMIT_FRAME_4MS = 0x00000020, /* 4msec tx burst limit */
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NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */
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};
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/* Bit masks for DFS per regdomain */
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enum {
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NO_DFS = 0x0000000000000000ULL, /* NB: must be zero */
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DFS_FCC3 = 0x0000000000000001ULL,
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DFS_ETSI = 0x0000000000000002ULL,
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DFS_MKK4 = 0x0000000000000004ULL,
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};
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enum { /* conformance test limits */
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FCC = 0x10,
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MKK = 0x40,
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ETSI = 0x30,
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};
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/*
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* THE following table is the mapping of regdomain pairs specified by
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* an 8 bit regdomain value to the individual unitary reg domains
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*/
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typedef struct regDomainPair {
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HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */
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HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */
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HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */
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uint32_t flags5GHz; /* Requirements flags (AdHoc
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disallow, noise floor cal needed,
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etc) */
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uint32_t flags2GHz; /* Requirements flags (AdHoc
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disallow, noise floor cal needed,
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etc) */
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uint64_t pscanMask; /* Passive Scan flags which
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can override unitary domain
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passive scan flags. This
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value is used as a mask on
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the unitary flags*/
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uint16_t singleCC; /* Country code of single country if
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a one-on-one mapping exists */
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} REG_DMN_PAIR_MAPPING;
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typedef struct {
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HAL_CTRY_CODE countryCode;
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HAL_REG_DOMAIN regDmnEnum;
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} COUNTRY_CODE_TO_ENUM_RD;
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/*
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* Frequency band collections are defined using bitmasks. Each bit
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* in a mask is the index of an entry in one of the following tables.
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* Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit
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* vectors must be enlarged or the tables split somehow (e.g. split
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* 1/2 and 1/4 rate channels into a separate table).
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*
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* Beware of ordering; the indices are defined relative to the preceding
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* entry so if things get off there will be confusion. A good way to
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* check the indices is to collect them in a switch statement in a stub
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* function so the compiler checks for duplicates.
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*/
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typedef struct {
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uint16_t lowChannel; /* Low channel center in MHz */
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uint16_t highChannel; /* High Channel center in MHz */
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uint8_t powerDfs; /* Max power (dBm) for channel
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range when using DFS */
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uint8_t antennaMax; /* Max allowed antenna gain */
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uint8_t channelBW; /* Bandwidth of the channel */
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uint8_t channelSep; /* Channel separation within
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the band */
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uint64_t useDfs; /* Use DFS in the RegDomain
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if corresponding bit is set */
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uint64_t usePassScan; /* Use Passive Scan in the RegDomain
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if corresponding bit is set */
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} REG_DMN_FREQ_BAND;
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typedef struct regDomain {
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uint16_t regDmnEnum; /* value from EnumRd table */
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uint8_t conformanceTestLimit;
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uint32_t flags; /* Requirement flags (AdHoc disallow,
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noise floor cal needed, etc) */
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uint64_t dfsMask; /* DFS bitmask for 5Ghz tables */
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uint64_t pscan; /* Bitmask for passive scan */
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chanbmask_t chan11a; /* 11a channels */
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chanbmask_t chan11a_turbo; /* 11a static turbo channels */
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chanbmask_t chan11a_dyn_turbo; /* 11a dynamic turbo channels */
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chanbmask_t chan11a_half; /* 11a 1/2 width channels */
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chanbmask_t chan11a_quarter; /* 11a 1/4 width channels */
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chanbmask_t chan11b; /* 11b channels */
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chanbmask_t chan11g; /* 11g channels */
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chanbmask_t chan11g_turbo; /* 11g dynamic turbo channels */
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chanbmask_t chan11g_half; /* 11g 1/2 width channels */
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chanbmask_t chan11g_quarter; /* 11g 1/4 width channels */
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} REG_DOMAIN;
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struct cmode {
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u_int mode;
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u_int flags;
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REG_DMN_FREQ_BAND *freqs;
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};
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#endif
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