757 lines
21 KiB
C
757 lines
21 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ah_desc.h" /* NB: for HAL_PHYERR* */
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ah_eeprom_v14.h" /* for owl_get_ntxchains() */
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/*
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* Return the wireless modes (a,b,g,n,t) supported by hardware.
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*
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* This value is what is actually supported by the hardware
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* and is unaffected by regulatory/country code settings.
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*
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*/
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u_int
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ar5416GetWirelessModes(struct ath_hal *ah)
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{
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u_int mode;
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struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
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HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
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mode = ar5212GetWirelessModes(ah);
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/* Only enable HT modes if the NIC supports HT */
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if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11A))
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mode |= HAL_MODE_11NA_HT20
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| HAL_MODE_11NA_HT40PLUS
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| HAL_MODE_11NA_HT40MINUS
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;
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if (pCap->halHTSupport == AH_TRUE && (mode & HAL_MODE_11G))
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mode |= HAL_MODE_11NG_HT20
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| HAL_MODE_11NG_HT40PLUS
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| HAL_MODE_11NG_HT40MINUS
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;
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return mode;
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}
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/*
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* Change the LED blinking pattern to correspond to the connectivity
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*/
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void
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ar5416SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
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{
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static const uint32_t ledbits[8] = {
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AR_MAC_LED_ASSOC_NONE, /* HAL_LED_INIT */
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AR_MAC_LED_ASSOC_PEND, /* HAL_LED_SCAN */
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AR_MAC_LED_ASSOC_PEND, /* HAL_LED_AUTH */
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AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC*/
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AR_MAC_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
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AR_MAC_LED_ASSOC_NONE,
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AR_MAC_LED_ASSOC_NONE,
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AR_MAC_LED_ASSOC_NONE,
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};
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if (AR_SREV_HOWL(ah))
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return;
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/*
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* Set the blink operating mode.
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*/
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OS_REG_RMW_FIELD(ah, AR_MAC_LED,
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AR_MAC_LED_ASSOC, ledbits[state & 0x7]);
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/* XXX Blink slow mode? */
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/* XXX Blink threshold? */
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/* XXX Blink sleep hystersis? */
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/*
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* Set the LED blink configuration to be proportional
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* to the current TX and RX filter bytes. (Ie, RX'ed
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* frames that don't match the filter are ignored.)
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* This means that higher TX/RX throughput will result
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* in the blink rate increasing.
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*/
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OS_REG_RMW_FIELD(ah, AR_MAC_LED, AR_MAC_LED_MODE,
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AR_MAC_LED_MODE_PROP);
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}
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/*
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* Get the current hardware tsf for stamlme
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*/
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uint64_t
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ar5416GetTsf64(struct ath_hal *ah)
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{
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uint32_t low1, low2, u32;
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/* sync multi-word read */
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low1 = OS_REG_READ(ah, AR_TSF_L32);
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u32 = OS_REG_READ(ah, AR_TSF_U32);
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low2 = OS_REG_READ(ah, AR_TSF_L32);
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if (low2 < low1) { /* roll over */
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/*
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* If we are not preempted this will work. If we are
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* then we re-reading AR_TSF_U32 does no good as the
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* low bits will be meaningless. Likewise reading
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* L32, U32, U32, then comparing the last two reads
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* to check for rollover doesn't help if preempted--so
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* we take this approach as it costs one less PCI read
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* which can be noticeable when doing things like
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* timestamping packets in monitor mode.
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*/
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u32++;
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}
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return (((uint64_t) u32) << 32) | ((uint64_t) low2);
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}
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/*
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* Update the TSF.
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*
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* The full TSF is only updated once the upper 32 bits have
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* been written. Writing only the lower 32 bits of the TSF
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* will not actually correctly update the TSF.
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*
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* The #if 0'ed code is to check whether the previous TSF
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* reset or write has completed before writing to the
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* TSF. Strictly speaking, it should be also checked before
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* reading the TSF as the write/reset may not have completed.
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*/
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void
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ar5416SetTsf64(struct ath_hal *ah, uint64_t tsf64)
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{
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/* XXX check if this is correct! */
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#if 0
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int i;
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uint32_t v;
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for (i = 0; i < 10; i++) {
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v = OS_REG_READ(ah, AR_SLP32_MODE);
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if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0)
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break;
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OS_DELAY(10);
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}
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if (i == 10)
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ath_hal_printf(ah, "%s: couldn't slew things right!\n", __func__);
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#endif
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OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
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OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
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}
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/*
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* Reset the current hardware tsf for stamlme.
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*/
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void
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ar5416ResetTsf(struct ath_hal *ah)
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{
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uint32_t v;
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int i;
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for (i = 0; i < 10; i++) {
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v = OS_REG_READ(ah, AR_SLP32_MODE);
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if ((v & AR_SLP32_TSF_WRITE_STATUS) == 0)
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break;
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OS_DELAY(10);
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}
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OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
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}
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uint32_t
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ar5416GetCurRssi(struct ath_hal *ah)
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{
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if (AR_SREV_OWL(ah))
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return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
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return (OS_REG_READ(ah, AR9130_PHY_CURRENT_RSSI) & 0xff);
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}
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HAL_BOOL
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ar5416SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
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{
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return AH_TRUE;
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}
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/* Setup decompression for given key index */
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HAL_BOOL
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ar5416SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
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{
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return AH_TRUE;
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}
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/* Setup coverage class */
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void
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ar5416SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
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{
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ar5212SetCoverageClass(ah, coverageclass, now);
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}
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/*
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* Return the busy for rx_frame, rx_clear, and tx_frame
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*/
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HAL_BOOL
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ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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u_int32_t good = AH_TRUE;
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/* XXX freeze/unfreeze mib counters */
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uint32_t rc = OS_REG_READ(ah, AR_RCCNT);
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uint32_t ec = OS_REG_READ(ah, AR_EXTRCCNT);
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uint32_t rf = OS_REG_READ(ah, AR_RFCNT);
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uint32_t tf = OS_REG_READ(ah, AR_TFCNT);
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uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
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if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cc) {
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/*
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* Cycle counter wrap (or initial call); it's not possible
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* to accurately calculate a value because the registers
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* right shift rather than wrap--so punt and return 0.
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*/
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: cycle counter wrap. ExtBusy = 0\n", __func__);
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good = AH_FALSE;
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} else {
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hsample->cycle_count = cc - ahp->ah_cycleCount;
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hsample->chan_busy = rc - ahp->ah_ctlBusy;
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hsample->ext_chan_busy = ec - ahp->ah_extBusy;
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hsample->rx_busy = rf - ahp->ah_rxBusy;
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hsample->tx_busy = tf - ahp->ah_txBusy;
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}
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/*
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* Keep a copy of the MIB results so the next sample has something
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* to work from.
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*/
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ahp->ah_cycleCount = cc;
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ahp->ah_rxBusy = rf;
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ahp->ah_ctlBusy = rc;
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ahp->ah_txBusy = tf;
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ahp->ah_extBusy = ec;
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return (good);
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}
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/*
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* Setup the TX/RX chainmasks - this needs to be done before a call
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* to the reset method as it doesn't update the hardware.
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*/
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void
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ar5416SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,
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uint32_t rx_chainmask)
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{
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HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
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AH5416(ah)->ah_tx_chainmask = tx_chainmask & pCap->halTxChainMask;
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AH5416(ah)->ah_rx_chainmask = rx_chainmask & pCap->halRxChainMask;
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}
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/*
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* Return approximation of extension channel busy over an time interval
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* 0% (clear) -> 100% (busy)
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*
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* XXX TODO: update this to correctly sample all the counters,
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* rather than a subset of it.
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*/
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uint32_t
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ar5416Get11nExtBusy(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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uint32_t busy; /* percentage */
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uint32_t cycleCount, ctlBusy, extBusy;
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ctlBusy = OS_REG_READ(ah, AR_RCCNT);
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extBusy = OS_REG_READ(ah, AR_EXTRCCNT);
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cycleCount = OS_REG_READ(ah, AR_CCCNT);
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if (ahp->ah_cycleCount == 0 || ahp->ah_cycleCount > cycleCount) {
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/*
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* Cycle counter wrap (or initial call); it's not possible
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* to accurately calculate a value because the registers
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* right shift rather than wrap--so punt and return 0.
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*/
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busy = 0;
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycle counter wrap. ExtBusy = 0\n",
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__func__);
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} else {
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uint32_t cycleDelta = cycleCount - ahp->ah_cycleCount;
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uint32_t ctlBusyDelta = ctlBusy - ahp->ah_ctlBusy;
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uint32_t extBusyDelta = extBusy - ahp->ah_extBusy;
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uint32_t ctlClearDelta = 0;
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/* Compute control channel rxclear.
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* The cycle delta may be less than the control channel delta.
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* This could be solved by freezing the timers (or an atomic read,
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* if one was available). Checking for the condition should be
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* sufficient.
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*/
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if (cycleDelta > ctlBusyDelta) {
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ctlClearDelta = cycleDelta - ctlBusyDelta;
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}
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/* Compute ratio of extension channel busy to control channel clear
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* as an approximation to extension channel cleanliness.
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*
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* According to the hardware folks, ext rxclear is undefined
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* if the ctrl rxclear is de-asserted (i.e. busy)
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*/
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if (ctlClearDelta) {
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busy = (extBusyDelta * 100) / ctlClearDelta;
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} else {
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busy = 100;
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}
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if (busy > 100) {
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busy = 100;
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}
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#if 0
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: cycleDelta 0x%x, ctlBusyDelta 0x%x, "
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"extBusyDelta 0x%x, ctlClearDelta 0x%x, "
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"busy %d\n",
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__func__, cycleDelta, ctlBusyDelta, extBusyDelta, ctlClearDelta, busy);
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#endif
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}
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ahp->ah_cycleCount = cycleCount;
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ahp->ah_ctlBusy = ctlBusy;
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ahp->ah_extBusy = extBusy;
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return busy;
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}
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/*
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* Configure 20/40 operation
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*
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* 20/40 = joint rx clear (control and extension)
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* 20 = rx clear (control)
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*
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* - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz when changing
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* from 20/40 => 20 only
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*/
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void
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ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
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{
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uint32_t macmode;
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/* Configure MAC for 20/40 operation */
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if (mode == HAL_HT_MACMODE_2040) {
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macmode = AR_2040_JOINED_RX_CLEAR;
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} else {
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macmode = 0;
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}
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OS_REG_WRITE(ah, AR_2040_MODE, macmode);
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}
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/*
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* Get Rx clear (control/extension channel)
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*
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* Returns active low (busy) for ctrl/ext channel
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* Owl 2.0
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*/
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HAL_HT_RXCLEAR
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ar5416Get11nRxClear(struct ath_hal *ah)
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{
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HAL_HT_RXCLEAR rxclear = 0;
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uint32_t val;
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val = OS_REG_READ(ah, AR_DIAG_SW);
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/* control channel */
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if (val & AR_DIAG_RXCLEAR_CTL_LOW) {
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rxclear |= HAL_RX_CLEAR_CTL_LOW;
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}
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/* extension channel */
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if (val & AR_DIAG_RXCLEAR_EXT_LOW) {
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rxclear |= HAL_RX_CLEAR_EXT_LOW;
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}
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return rxclear;
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}
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/*
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* Set Rx clear (control/extension channel)
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*
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* Useful for forcing the channel to appear busy for
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* debugging/diagnostics
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* Owl 2.0
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*/
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void
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ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
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{
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/* control channel */
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if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
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OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
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} else {
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_CTL_LOW);
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}
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/* extension channel */
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if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
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OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
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} else {
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RXCLEAR_EXT_LOW);
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}
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}
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/* XXX shouldn't be here! */
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#define TU_TO_USEC(_tu) ((_tu) << 10)
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HAL_STATUS
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ar5416SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,
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uint32_t nextStart, HAL_QUIET_FLAG flag)
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{
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uint32_t period_us = TU_TO_USEC(period); /* convert to us unit */
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uint32_t nextStart_us = TU_TO_USEC(nextStart); /* convert to us unit */
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if (flag & HAL_QUIET_ENABLE) {
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if ((!nextStart) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
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/* Add the nextStart offset to the current TSF */
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nextStart_us += OS_REG_READ(ah, AR_TSF_L32);
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}
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if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
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nextStart_us += ah->ah_config.ah_sw_beacon_response_time;
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}
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OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
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OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
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OS_REG_WRITE(ah, AR_QUIET_PERIOD, period_us);
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OS_REG_WRITE(ah, AR_NEXT_QUIET, nextStart_us);
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OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
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} else {
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OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_TIMER_MODE_QUIET);
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}
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return HAL_OK;
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}
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#undef TU_TO_USEC
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HAL_STATUS
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ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
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uint32_t capability, uint32_t *result)
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{
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switch (type) {
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case HAL_CAP_BB_HANG:
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switch (capability) {
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case HAL_BB_HANG_RIFS:
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return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP;
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case HAL_BB_HANG_DFS:
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return (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ? HAL_OK : HAL_ENOTSUPP;
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case HAL_BB_HANG_RX_CLEAR:
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return AR_SREV_MERLIN(ah) ? HAL_OK : HAL_ENOTSUPP;
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}
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break;
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case HAL_CAP_MAC_HANG:
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return ((ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) ||
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(ah->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE) ||
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AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) ?
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HAL_OK : HAL_ENOTSUPP;
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case HAL_CAP_DIVERSITY: /* disable classic fast diversity */
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return HAL_ENXIO;
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case HAL_CAP_ENFORCE_TXOP:
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if (capability == 0)
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return (HAL_OK);
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if (capability != 1)
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return (HAL_ENOTSUPP);
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(*result) =
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!! (AH5212(ah)->ah_miscMode & AR_PCU_TXOP_TBTT_LIMIT_ENA);
|
|
return (HAL_OK);
|
|
default:
|
|
break;
|
|
}
|
|
return ar5212GetCapability(ah, type, capability, result);
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5416SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
|
u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
|
|
{
|
|
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
|
|
|
|
switch (type) {
|
|
case HAL_CAP_RX_CHAINMASK:
|
|
setting &= ath_hal_eepromGet(ah, AR_EEP_RXMASK, NULL);
|
|
pCap->halRxChainMask = setting;
|
|
if (owl_get_ntxchains(setting) > 2)
|
|
pCap->halRxStreams = 2;
|
|
else
|
|
pCap->halRxStreams = 1;
|
|
return AH_TRUE;
|
|
case HAL_CAP_TX_CHAINMASK:
|
|
setting &= ath_hal_eepromGet(ah, AR_EEP_TXMASK, NULL);
|
|
pCap->halTxChainMask = setting;
|
|
if (owl_get_ntxchains(setting) > 2)
|
|
pCap->halTxStreams = 2;
|
|
else
|
|
pCap->halTxStreams = 1;
|
|
return AH_TRUE;
|
|
case HAL_CAP_ENFORCE_TXOP:
|
|
if (capability != 1)
|
|
return AH_FALSE;
|
|
if (setting) {
|
|
AH5212(ah)->ah_miscMode
|
|
|= AR_PCU_TXOP_TBTT_LIMIT_ENA;
|
|
OS_REG_SET_BIT(ah, AR_MISC_MODE,
|
|
AR_PCU_TXOP_TBTT_LIMIT_ENA);
|
|
} else {
|
|
AH5212(ah)->ah_miscMode
|
|
&= ~AR_PCU_TXOP_TBTT_LIMIT_ENA;
|
|
OS_REG_CLR_BIT(ah, AR_MISC_MODE,
|
|
AR_PCU_TXOP_TBTT_LIMIT_ENA);
|
|
}
|
|
return AH_TRUE;
|
|
default:
|
|
break;
|
|
}
|
|
return ar5212SetCapability(ah, type, capability, setting, status);
|
|
}
|
|
|
|
static int ar5416DetectMacHang(struct ath_hal *ah);
|
|
static int ar5416DetectBBHang(struct ath_hal *ah);
|
|
|
|
HAL_BOOL
|
|
ar5416GetDiagState(struct ath_hal *ah, int request,
|
|
const void *args, uint32_t argsize,
|
|
void **result, uint32_t *resultsize)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
int hangs;
|
|
|
|
if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
|
|
return AH_TRUE;
|
|
switch (request) {
|
|
case HAL_DIAG_EEPROM:
|
|
return ath_hal_eepromDiag(ah, request,
|
|
args, argsize, result, resultsize);
|
|
case HAL_DIAG_CHECK_HANGS:
|
|
if (argsize != sizeof(int))
|
|
return AH_FALSE;
|
|
hangs = *(const int *) args;
|
|
ahp->ah_hangs = 0;
|
|
if (hangs & HAL_BB_HANGS)
|
|
ahp->ah_hangs |= ar5416DetectBBHang(ah);
|
|
/* NB: if BB is hung MAC will be hung too so skip check */
|
|
if (ahp->ah_hangs == 0 && (hangs & HAL_MAC_HANGS))
|
|
ahp->ah_hangs |= ar5416DetectMacHang(ah);
|
|
*result = &ahp->ah_hangs;
|
|
*resultsize = sizeof(ahp->ah_hangs);
|
|
return AH_TRUE;
|
|
}
|
|
return ar5212GetDiagState(ah, request,
|
|
args, argsize, result, resultsize);
|
|
}
|
|
|
|
HAL_BOOL
|
|
ar5416SetRifsDelay(struct ath_hal *ah, const struct ieee80211_channel *chan,
|
|
HAL_BOOL enable)
|
|
{
|
|
uint32_t val;
|
|
HAL_BOOL is_chan_2g = AH_FALSE;
|
|
HAL_BOOL is_ht40 = AH_FALSE;
|
|
|
|
if (chan)
|
|
is_chan_2g = IEEE80211_IS_CHAN_2GHZ(chan);
|
|
|
|
if (chan)
|
|
is_ht40 = IEEE80211_IS_CHAN_HT40(chan);
|
|
|
|
/* Only support disabling RIFS delay for now */
|
|
HALASSERT(enable == AH_FALSE);
|
|
|
|
if (enable == AH_TRUE)
|
|
return AH_FALSE;
|
|
|
|
/* Change RIFS init delay to 0 */
|
|
val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
|
|
val &= ~AR_PHY_RIFS_INIT_DELAY;
|
|
OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
|
|
|
|
/*
|
|
* For Owl, RIFS RX parameters are controlled differently;
|
|
* it isn't enabled in the inivals by default.
|
|
*
|
|
* For Sowl/Howl, RIFS RX is enabled in the inivals by default;
|
|
* the following code sets them back to non-RIFS values.
|
|
*
|
|
* For > Sowl/Howl, RIFS RX can be left on by default and so
|
|
* this function shouldn't be called.
|
|
*/
|
|
if ((! AR_SREV_SOWL(ah)) && (! AR_SREV_HOWL(ah)))
|
|
return AH_TRUE;
|
|
|
|
/* Reset search delay to default values */
|
|
if (is_chan_2g)
|
|
if (is_ht40)
|
|
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x268);
|
|
else
|
|
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x134);
|
|
else
|
|
if (is_ht40)
|
|
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x370);
|
|
else
|
|
OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, 0x1b8);
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
static HAL_BOOL
|
|
ar5416CompareDbgHang(struct ath_hal *ah, const mac_dbg_regs_t *regs,
|
|
const hal_mac_hang_check_t *check)
|
|
{
|
|
int found_states;
|
|
|
|
found_states = 0;
|
|
if (check->states & dcu_chain_state) {
|
|
int i;
|
|
|
|
for (i = 0; i < 6; i++) {
|
|
if (((regs->dma_dbg_4 >> (5*i)) & 0x1f) ==
|
|
check->dcu_chain_state)
|
|
found_states |= dcu_chain_state;
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
if (((regs->dma_dbg_5 >> (5*i)) & 0x1f) ==
|
|
check->dcu_chain_state)
|
|
found_states |= dcu_chain_state;
|
|
}
|
|
}
|
|
if (check->states & dcu_complete_state) {
|
|
if ((regs->dma_dbg_6 & 0x3) == check->dcu_complete_state)
|
|
found_states |= dcu_complete_state;
|
|
}
|
|
if (check->states & qcu_stitch_state) {
|
|
if (((regs->dma_dbg_3 >> 18) & 0xf) == check->qcu_stitch_state)
|
|
found_states |= qcu_stitch_state;
|
|
}
|
|
if (check->states & qcu_fetch_state) {
|
|
if (((regs->dma_dbg_3 >> 22) & 0xf) == check->qcu_fetch_state)
|
|
found_states |= qcu_fetch_state;
|
|
}
|
|
if (check->states & qcu_complete_state) {
|
|
if (((regs->dma_dbg_3 >> 26) & 0x7) == check->qcu_complete_state)
|
|
found_states |= qcu_complete_state;
|
|
}
|
|
return (found_states == check->states);
|
|
}
|
|
|
|
#define NUM_STATUS_READS 50
|
|
|
|
static int
|
|
ar5416DetectMacHang(struct ath_hal *ah)
|
|
{
|
|
static const hal_mac_hang_check_t hang_sig1 = {
|
|
.dcu_chain_state = 0x6,
|
|
.dcu_complete_state = 0x1,
|
|
.states = dcu_chain_state
|
|
| dcu_complete_state,
|
|
};
|
|
static const hal_mac_hang_check_t hang_sig2 = {
|
|
.qcu_stitch_state = 0x9,
|
|
.qcu_fetch_state = 0x8,
|
|
.qcu_complete_state = 0x4,
|
|
.states = qcu_stitch_state
|
|
| qcu_fetch_state
|
|
| qcu_complete_state,
|
|
};
|
|
mac_dbg_regs_t mac_dbg;
|
|
int i;
|
|
|
|
mac_dbg.dma_dbg_3 = OS_REG_READ(ah, AR_DMADBG_3);
|
|
mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
|
|
mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
|
|
mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
|
|
for (i = 1; i <= NUM_STATUS_READS; i++) {
|
|
if (mac_dbg.dma_dbg_3 != OS_REG_READ(ah, AR_DMADBG_3) ||
|
|
mac_dbg.dma_dbg_4 != OS_REG_READ(ah, AR_DMADBG_4) ||
|
|
mac_dbg.dma_dbg_5 != OS_REG_READ(ah, AR_DMADBG_5) ||
|
|
mac_dbg.dma_dbg_6 != OS_REG_READ(ah, AR_DMADBG_6))
|
|
return 0;
|
|
}
|
|
|
|
if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig1))
|
|
return HAL_MAC_HANG_SIG1;
|
|
if (ar5416CompareDbgHang(ah, &mac_dbg, &hang_sig2))
|
|
return HAL_MAC_HANG_SIG2;
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown MAC hang signature "
|
|
"DMADBG_3=0x%x DMADBG_4=0x%x DMADBG_5=0x%x DMADBG_6=0x%x\n",
|
|
__func__, mac_dbg.dma_dbg_3, mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
|
|
mac_dbg.dma_dbg_6);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Determine if the baseband using the Observation Bus Register
|
|
*/
|
|
static int
|
|
ar5416DetectBBHang(struct ath_hal *ah)
|
|
{
|
|
#define N(a) (sizeof(a)/sizeof(a[0]))
|
|
/*
|
|
* Check the PCU Observation Bus 1 register (0x806c)
|
|
* NUM_STATUS_READS times
|
|
*
|
|
* 4 known BB hang signatures -
|
|
* [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
|
|
* [2] bits 8,9 are 1, bit 11 is 0. State machine state
|
|
* (bits 25-31) is 0x52
|
|
* [3] bits 8,9 are 1, bit 11 is 0. State machine state
|
|
* (bits 25-31) is 0x18
|
|
* [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
|
|
* Rx State (bits 20-24) is 0x7.
|
|
*/
|
|
static const struct {
|
|
uint32_t val;
|
|
uint32_t mask;
|
|
int code;
|
|
} hang_list[] = {
|
|
/* Reg Value Reg Mask Hang Code XXX */
|
|
{ 0x1E000000, 0x7E000B00, HAL_BB_HANG_DFS },
|
|
{ 0x52000B00, 0x7E000B00, HAL_BB_HANG_RIFS },
|
|
{ 0x18000B00, 0x7E000B00, HAL_BB_HANG_RX_CLEAR },
|
|
{ 0x00702400, 0x7E7FFFEF, HAL_BB_HANG_RX_CLEAR }
|
|
};
|
|
uint32_t hang_sig;
|
|
int i;
|
|
|
|
hang_sig = OS_REG_READ(ah, AR_OBSERV_1);
|
|
for (i = 1; i <= NUM_STATUS_READS; i++) {
|
|
if (hang_sig != OS_REG_READ(ah, AR_OBSERV_1))
|
|
return 0;
|
|
}
|
|
for (i = 0; i < N(hang_list); i++)
|
|
if ((hang_sig & hang_list[i].mask) == hang_list[i].val) {
|
|
HALDEBUG(ah, HAL_DEBUG_HANG,
|
|
"%s BB hang, signature 0x%x, code 0x%x\n",
|
|
__func__, hang_sig, hang_list[i].code);
|
|
return hang_list[i].code;
|
|
}
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_HANG, "%s Found an unknown BB hang signature! "
|
|
"<0x806c>=0x%x\n", __func__, hang_sig);
|
|
|
|
return 0;
|
|
#undef N
|
|
}
|
|
#undef NUM_STATUS_READS
|