e3fd0bc1b2
Most part is merged from amd64. - i386/acpica/acpi_wakecode.S Replaced with amd64 code (from realmode to paging enabling code). - i386/acpica/acpi_wakeup.c Replaced with amd64 code (except for wakeup_pagetables stuff). - i386/include/pcb.h - i386/i386/genassym.c Added PCB new members (CR0, CR2, CR4, DS, ED, FS, SS, GDT, IDT, LDT and TR) needed for suspend/resume, not for context switch. - i386/i386/swtch.s Added suspendctx() and resumectx(). Note that savectx() was not changed and used for suspending (while amd64 code uses it). BSP and AP execute the same sequence, suspendctx(), acpi_wakecode() and resumectx() for suspend/resume (in case of UP system also). - i386/i386/apic_vector.s Added cpususpend(). - i386/i386/mp_machdep.c - i386/include/smp.h Added cpususpend_handler(). - i386/include/apicvar.h - kern/subr_smp.c - sys/smp.h Added IPI_SUSPEND and suspend_cpus(). - i386/i386/initcpu.c - i386/i386/machdep.c - i386/include/md_var.h - pc98/pc98/machdep.c Moved initializecpu() declarations to md_var.h. MFC after: 3 days
232 lines
8.8 KiB
C
232 lines
8.8 KiB
C
/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_APICVAR_H_
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#define _MACHINE_APICVAR_H_
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/*
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* Local && I/O APIC variable definitions.
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*/
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/*
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* Layout of local APIC interrupt vectors:
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*
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* 0xff (255) +-------------+
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* | | 15 (Spurious / IPIs / Local Interrupts)
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* 0xf0 (240) +-------------+
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* | | 14 (I/O Interrupts / Timer)
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* 0xe0 (224) +-------------+
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* | | 13 (I/O Interrupts)
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* 0xd0 (208) +-------------+
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* | | 12 (I/O Interrupts)
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* 0xc0 (192) +-------------+
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* | | 11 (I/O Interrupts)
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* 0xb0 (176) +-------------+
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* | | 10 (I/O Interrupts)
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* 0xa0 (160) +-------------+
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* | | 9 (I/O Interrupts)
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* 0x90 (144) +-------------+
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* | | 8 (I/O Interrupts / System Calls)
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* 0x80 (128) +-------------+
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* | | 7 (I/O Interrupts)
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* 0x70 (112) +-------------+
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* | | 6 (I/O Interrupts)
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* 0x60 (96) +-------------+
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* | | 5 (I/O Interrupts)
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* 0x50 (80) +-------------+
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* | | 4 (I/O Interrupts)
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* 0x40 (64) +-------------+
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* | | 3 (I/O Interrupts)
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* 0x30 (48) +-------------+
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* | | 2 (ATPIC Interrupts)
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* 0x20 (32) +-------------+
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* | | 1 (Exceptions, traps, faults, etc.)
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* 0x10 (16) +-------------+
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* | | 0 (Exceptions, traps, faults, etc.)
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* 0x00 (0) +-------------+
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*
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* Note: 0x80 needs to be handled specially and not allocated to an
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* I/O device!
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*/
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#define MAX_APIC_ID 0xfe
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#define APIC_ID_ALL 0xff
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/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
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#define APIC_IO_INTS (IDT_IO_INTS + 16)
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#define APIC_NUM_IOINTS 191
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/* The timer interrupt is used for clock handling and drives hardclock, etc. */
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#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
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/*
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********************* !!! WARNING !!! ******************************
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* Each local apic has an interrupt receive fifo that is two entries deep
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* for each interrupt priority class (higher 4 bits of interrupt vector).
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* Once the fifo is full the APIC can no longer receive interrupts for this
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* class and sending IPIs from other CPUs will be blocked.
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* To avoid deadlocks there should be no more than two IPI interrupts
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* pending at the same time.
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* Currently this is guaranteed by dividing the IPIs in two groups that have
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* each at most one IPI interrupt pending. The first group is protected by the
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* smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
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* at a time) The second group uses a single interrupt and a bitmap to avoid
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* redundant IPI interrupts.
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*/
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/* Interrupts for local APIC LVT entries other than the timer. */
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#define APIC_LOCAL_INTS 240
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#define APIC_ERROR_INT APIC_LOCAL_INTS
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#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
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#define APIC_CMC_INT (APIC_LOCAL_INTS + 2)
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#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3)
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#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
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#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
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#define IPI_INVLPG (APIC_IPI_INTS + 2)
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#define IPI_INVLRNG (APIC_IPI_INTS + 3)
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#define IPI_INVLCACHE (APIC_IPI_INTS + 4)
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#define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */
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/* Vector to handle bitmap based IPIs */
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#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6)
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/* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
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#define IPI_AST 0 /* Generate software trap. */
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#define IPI_PREEMPT 1
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#define IPI_HARDCLOCK 2
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#define IPI_BITMAP_LAST IPI_HARDCLOCK
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#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
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#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
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#define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */
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#define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */
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/*
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* The spurious interrupt can share the priority class with the IPIs since
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* it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
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*/
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#define APIC_SPURIOUS_INT 255
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#define LVT_LINT0 0
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#define LVT_LINT1 1
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#define LVT_TIMER 2
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#define LVT_ERROR 3
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#define LVT_PMC 4
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#define LVT_THERMAL 5
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#define LVT_CMCI 6
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#define LVT_MAX LVT_CMCI
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#ifndef LOCORE
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#define APIC_IPI_DEST_SELF -1
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#define APIC_IPI_DEST_ALL -2
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#define APIC_IPI_DEST_OTHERS -3
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#define APIC_BUS_UNKNOWN -1
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#define APIC_BUS_ISA 0
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#define APIC_BUS_EISA 1
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#define APIC_BUS_PCI 2
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#define APIC_BUS_MAX APIC_BUS_PCI
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/*
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* An APIC enumerator is a psuedo bus driver that enumerates APIC's including
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* CPU's and I/O APIC's.
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*/
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struct apic_enumerator {
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const char *apic_name;
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int (*apic_probe)(void);
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int (*apic_probe_cpus)(void);
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int (*apic_setup_local)(void);
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int (*apic_setup_io)(void);
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SLIST_ENTRY(apic_enumerator) apic_next;
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};
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inthand_t
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IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
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IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
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IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
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IDTVEC(spuriousint), IDTVEC(timerint);
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extern vm_paddr_t lapic_paddr;
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extern int apic_cpuids[];
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u_int apic_alloc_vector(u_int apic_id, u_int irq);
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u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count,
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u_int align);
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void apic_disable_vector(u_int apic_id, u_int vector);
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void apic_enable_vector(u_int apic_id, u_int vector);
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void apic_free_vector(u_int apic_id, u_int vector, u_int irq);
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u_int apic_idt_to_irq(u_int apic_id, u_int vector);
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void apic_register_enumerator(struct apic_enumerator *enumerator);
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u_int apic_cpuid(u_int apic_id);
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void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
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int ioapic_disable_pin(void *cookie, u_int pin);
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int ioapic_get_vector(void *cookie, u_int pin);
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void ioapic_register(void *cookie);
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int ioapic_remap_vector(void *cookie, u_int pin, int vector);
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int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
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int ioapic_set_extint(void *cookie, u_int pin);
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int ioapic_set_nmi(void *cookie, u_int pin);
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int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
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int ioapic_set_triggermode(void *cookie, u_int pin,
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enum intr_trigger trigger);
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int ioapic_set_smi(void *cookie, u_int pin);
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void lapic_create(u_int apic_id, int boot_cpu);
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void lapic_disable(void);
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void lapic_disable_pmc(void);
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void lapic_dump(const char *str);
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void lapic_enable_cmc(void);
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int lapic_enable_pmc(void);
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void lapic_eoi(void);
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int lapic_id(void);
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void lapic_init(vm_paddr_t addr);
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int lapic_intr_pending(u_int vector);
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void lapic_ipi_raw(register_t icrlo, u_int dest);
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void lapic_ipi_vectored(u_int vector, int dest);
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int lapic_ipi_wait(int delay);
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void lapic_handle_cmc(void);
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void lapic_handle_error(void);
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void lapic_handle_intr(int vector, struct trapframe *frame);
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void lapic_handle_timer(struct trapframe *frame);
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void lapic_reenable_pmc(void);
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void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
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int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
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int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
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int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
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enum intr_polarity pol);
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int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
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enum intr_trigger trigger);
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void lapic_set_tpr(u_int vector);
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void lapic_setup(int boot);
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#endif /* !LOCORE */
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#endif /* _MACHINE_APICVAR_H_ */
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