1def609a63
all host controllers at the same time, we avoid problems where the BIOS will actually write to the USB registers of all the USB host controllers every time we handover one of them, and consequently reset the OS programmed values. Submitted by: avg Reviewed by: jhb
175 lines
8.2 KiB
C
175 lines
8.2 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EHCIREG_H_
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#define _EHCIREG_H_
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/* PCI config registers */
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#define PCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_INTERFACE_EHCI 0x20
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#define PCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USB_REV_MASK 0xff
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#define PCI_USB_REV_PRE_1_0 0x00
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#define PCI_USB_REV_1_0 0x10
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#define PCI_USB_REV_1_1 0x11
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#define PCI_USB_REV_2_0 0x20
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#define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */
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#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
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/* EHCI Extended Capabilities */
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#define EHCI_EC_LEGSUP 0x01
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#define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff)
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#define EHCI_EECP_ID(x) ((x) & 0xff)
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/* Legacy support extended capability */
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#define EHCI_LEGSUP_BIOS_SEM 0x02
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#define EHCI_LEGSUP_OS_SEM 0x03
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#define EHCI_LEGSUP_USBLEGCTLSTS 0x04
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/* EHCI capability registers */
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#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */
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/* reserved 0x01 */
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#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
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#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
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#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
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#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
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#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
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#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
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#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
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#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
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#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */
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#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
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#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
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#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
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#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
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#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
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#define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */
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/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */
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#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */
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#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
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#define EHCI_CMD_ITC_1 0x00010000
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#define EHCI_CMD_ITC_2 0x00020000
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#define EHCI_CMD_ITC_4 0x00040000
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#define EHCI_CMD_ITC_8 0x00080000
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#define EHCI_CMD_ITC_16 0x00100000
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#define EHCI_CMD_ITC_32 0x00200000
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#define EHCI_CMD_ITC_64 0x00400000
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#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
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#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
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#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
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#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door
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* bell */
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#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
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#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
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#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */
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#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
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#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
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#define EHCI_CMD_RS 0x00000001 /* RW run/stop */
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#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */
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#define EHCI_STS_ASS 0x00008000 /* RO async sched status */
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#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
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#define EHCI_STS_REC 0x00002000 /* RO reclamation */
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#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
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#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
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#define EHCI_STS_HSE 0x00000010 /* RWC host system error */
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#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
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#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
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#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
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#define EHCI_STS_INT 0x00000001 /* RWC interrupt */
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#define EHCI_STS_INTRS(x) ((x) & 0x3f)
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/*
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* NOTE: the doorbell interrupt is enabled, but the doorbell is never
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* used! SiS chipsets require this.
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*/
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#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | \
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EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
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#define EHCI_USBINTR 0x08 /* RW Interrupt register */
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#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance
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* ena */
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#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
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#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
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#define EHCI_INTR_PCIE 0x00000004 /* port change ena */
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#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
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#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
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#define EHCI_FRINDEX 0x0c /* RW Frame Index register */
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#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
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#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */
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#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */
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#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */
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#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
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#define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */
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#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
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#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
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#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
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#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
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#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
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#define EHCI_PS_PO 0x00002000 /* RW port owner */
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#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
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#define EHCI_PS_LS 0x00000c00 /* RO line status */
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#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
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#define EHCI_PS_PR 0x00000100 /* RW port reset */
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#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
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#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
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#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
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#define EHCI_PS_OCA 0x00000010 /* RO over current active */
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#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
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#define EHCI_PS_PE 0x00000004 /* RW port enable */
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#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
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#define EHCI_PS_CS 0x00000001 /* RO connect status */
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#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
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#define EHCI_USBMODE 0x68 /* RW USB Device mode register */
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#define EHCI_UM_CM 0x00000003 /* R/WO Controller Mode */
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#define EHCI_UM_CM_IDLE 0x0 /* Idle */
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#define EHCI_UM_CM_HOST 0x3 /* Host Controller */
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#define EHCI_UM_ES 0x00000004 /* R/WO Endian Select */
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#define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */
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#define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */
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#define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */
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#define EHCI_PORT_RESET_COMPLETE 2 /* ms */
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#endif /* _EHCIREG_H_ */
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