718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
204 lines
8.3 KiB
C
204 lines
8.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 Joachim Kuebart <joachim.kuebart@gmx.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* This supports the ENSONIQ AudioPCI board based on the ES1370. */
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#ifndef _ES1370_REG_H
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#define _ES1370_REG_H
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#define ES1370_REG_CONTROL 0x00
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#define ES1370_REG_STATUS 0x04
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#define ES1370_REG_UART_DATA 0x08
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#define ES1370_REG_UART_STATUS 0x09
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#define ES1370_REG_UART_CONTROL 0x09
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#define ES1370_REG_UART_TEST 0x0a
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#define ES1370_REG_MEMPAGE 0x0c
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#define ES1370_REG_CODEC 0x10
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#define CODEC_INDEX_SHIFT 8
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#define ES1370_REG_SERIAL_CONTROL 0x20
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#define ES1370_REG_DAC1_SCOUNT 0x24
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#define ES1370_REG_DAC2_SCOUNT 0x28
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#define ES1370_REG_ADC_SCOUNT 0x2c
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#define ES1370_REG_DAC1_FRAMEADR 0xc30
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#define ES1370_REG_DAC1_FRAMECNT 0xc34
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#define ES1370_REG_DAC2_FRAMEADR 0xc38
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#define ES1370_REG_DAC2_FRAMECNT 0xc3c
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#define ES1370_REG_ADC_FRAMEADR 0xd30
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#define ES1370_REG_ADC_FRAMECNT 0xd34
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#define DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)
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#define DAC2_DIVTOSR(x) (1411200 / ((x) + 2))
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#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
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#define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */
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#define CTRL_OPEN 0x20000000 /* no function, can be read and
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* written */
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#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
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#define CTRL_SH_PCLKDIV 16
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#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1
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* = I2S */
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#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
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#define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025,
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* 2=22050, 3=44100 */
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#define CTRL_SH_WTSRSEL 12
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#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
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#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
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#define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 =
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* MPEG */
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#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
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#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
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#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
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#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
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#define CTRL_ADC_EN 0x00000010 /* enable ADC */
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#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
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#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably
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* at address 0x200) */
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#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
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#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
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#define SCTRL_P2ENDINC 0x00380000 /* */
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#define SCTRL_SH_P2ENDINC 19
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#define SCTRL_P2STINC 0x00070000 /* */
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#define SCTRL_SH_P2STINC 16
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#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
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#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
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#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
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#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
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#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
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#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
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#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
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#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
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#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for
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* DAC1 */
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#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample
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* when disabled */
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#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
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#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
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#define SCTRL_R1FMT 0x00000030 /* format mask */
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#define SCTRL_SH_R1FMT 4
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#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
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#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
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#define SCTRL_P2FMT 0x0000000c /* format mask */
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#define SCTRL_SH_P2FMT 2
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#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
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#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
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#define SCTRL_P1FMT 0x00000003 /* format mask */
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#define SCTRL_SH_P1FMT 0
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#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
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#define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in
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* progress */
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#define STAT_CBUSY 0x00000200 /* 1 = codec busy */
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#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
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#define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2,
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* 2=ADC, 3=undef */
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#define STAT_SH_VC 5
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#define STAT_MCCB 0x00000010 /* CCB int pending */
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#define STAT_UART 0x00000008 /* UART int pending */
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#define STAT_DAC1 0x00000004 /* DAC1 int pending */
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#define STAT_DAC2 0x00000002 /* DAC2 int pending */
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#define STAT_ADC 0x00000001 /* ADC int pending */
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#define CODEC_OMIX1 0x10
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#define CODEC_OMIX2 0x11
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#define CODEC_LIMIX1 0x12
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#define CODEC_RIMIX1 0x13
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#define CODEC_LIMIX2 0x14
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#define CODEC_RIMIX2 0x15
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#define CODEC_RES_PD 0x16
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#define CODEC_CSEL 0x17
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#define CODEC_ADSEL 0x18
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#define CODEC_MGAIN 0x19
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/* ES1371 specific */
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#define CODEC_ID_SESHIFT 10
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#define CODEC_ID_SEMASK 0x1f
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#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
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#define CODEC_PIADD_MASK 0x007f0000
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#define CODEC_PIADD_SHIFT 16
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#define CODEC_PIDAT_MASK 0x0000ffff
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#define CODEC_PIDAT_SHIFT 0
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#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
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#define CODEC_POADD_MASK 0x007f0000
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#define CODEC_POADD_SHIFT 16
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#define CODEC_PODAT_MASK 0x0000ffff
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#define CODEC_PODAT_SHIFT 0
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#define CODEC_RDY 0x80000000 /* AC97 read data valid */
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#define CODEC_WIP 0x40000000 /* AC97 write in progress */
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#define ES1370_REG_CONTROL 0x00
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#define ES1370_REG_SERIAL_CONTROL 0x20
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#define ES1371_REG_CODEC 0x14
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#define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */
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#define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
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#define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */
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#define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */
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#define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */
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#define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
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#define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */
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#define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
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#define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
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#define ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
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#define ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
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#define ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
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/*
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* S/PDIF specific
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*/
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/* Use ES1370_REG_CONTROL */
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#define RECEN_B 0x08000000 /* Used to control mixing of analog with digital data */
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#define SPDIFEN_B 0x04000000 /* Reset to switch digital output mux to "THRU" mode */
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/* Use ES1370_REG_STATUS */
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#define ENABLE_SPDIF 0x00040000 /* Used to enable the S/PDIF circuitry */
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#define TEST_SPDIF 0x00020000 /* Used to put the S/PDIF module in "test mode" */
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/*
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* Sample rate converter addresses
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*/
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#define ES_SMPREG_DAC1 0x70
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#define ES_SMPREG_DAC2 0x74
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#define ES_SMPREG_ADC 0x78
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#define ES_SMPREG_TRUNC_N 0x00
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#define ES_SMPREG_INT_REGS 0x01
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#define ES_SMPREG_VFREQ_FRAC 0x03
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#define ES_SMPREG_VOL_ADC 0x6c
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#define ES_SMPREG_VOL_DAC1 0x7c
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#define ES_SMPREG_VOL_DAC2 0x7e
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#endif
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