8a7b91802a
* Support for AlphaStation 200, 250, 255, 400 * Untested support for UDB, Multia, AXPpci33 (Noname) * Support for Personal Workstation 433a/433au, 500a/500au, 600a/600au (Miata) * Some minor fixes and improvements to interrupt handling. Submitted by: Andrew Gallatin <gallatin@cs.duke.edu> (AS200, Miata) Obtained from: NetBSD (some code for AS200, Miata, Noname)
96 lines
4.0 KiB
C
96 lines
4.0 KiB
C
/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */
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/*
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* Copyright (c) 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Authors: Jeffrey Hsu, Jason R. Thorpe
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* 21066 chip registers
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*/
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#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
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#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r))
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/*
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* Base addresses
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*/
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#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */
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#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */
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#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */
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#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */
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#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */
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#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */
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#define IOC_HAE_ADDREXT 0x00000000f8000000UL
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#define IOC_HAE_RSVSD 0xffffffff07ffffffUL
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#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */
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#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */
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#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */
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#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */
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#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */
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#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */
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#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */
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#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */
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#define IOC_STAT0_CODESHIFT 8
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#define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */
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#define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */
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#define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */
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#define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */
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#define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */
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#define IOC_TB_ENA_TEN 0x0000000000000080UL
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#define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100) /* Window Base */
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#define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140) /* Window Mask */
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#define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */
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#define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */
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#define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160) /* Window Mask */
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#define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */
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#define IOC_W_BASE_W_BASE 0x00000000fff00000UL /* Window base value */
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#define IOC_W_BASE_SG 0x0000000100000000UL /* Window uses SGMAPs */
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#define IOC_W_BASE_WEN 0x0000000200000000UL /* Window enable */
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#define IOC_W_MASK_1M 0x0000000000000000UL /* 1MB window */
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#define IOC_W_MASK_2M 0x0000000000100000UL /* 2MB window */
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#define IOC_W_MASK_4M 0x0000000000300000UL /* 4MB window */
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#define IOC_W_MASK_8M 0x0000000000700000UL /* 8MB window */
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#define IOC_W_MASK_16M 0x0000000000f00000UL /* 16MB window */
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#define IOC_W_MASK_32M 0x0000000001f00000UL /* 32MB window */
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#define IOC_W_MASK_64M 0x0000000003f00000UL /* 64MB window */
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#define IOC_W_MASK_128M 0x0000000007f00000UL /* 128M window */
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#define IOC_W_MASK_256M 0x000000000ff00000UL /* 256M window */
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#define IOC_W_MASK_512M 0x000000001ff00000UL /* 512M window */
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#define IOC_W_MASK_1G 0x000000003ff00000UL /* 1GB window */
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#define IOC_W_MASK_2G 0x000000007ff00000UL /* 2GB window */
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#define IOC_W_MASK_4G 0x00000000fff00000UL /* 4GB window */
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#define IOC_W_T_BASE 0x00000000fffffc00UL /* page table base */
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