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and Braswell eMMC and SDXC controllers share the same IDs. Like in the PCI case, Braswell eMMC needs the SDHCI_QUIRK_DATA_TIMEOUT_1MHZ quirk (see r311794 for the corresponding change to the sdhci(4) PCI PCI front-end), though. However, due to the shared ACPI IDs, this is trickier to do. - Intel Apollo Lake eMMC and SDXC controllers are affected by the APL18 ("Using 32-bit Addressing Mode With SD/eMMC Controller May Lead to Unpredictable System Behavior") silicon bug [1]. When this erratum hits, typically both SDHCI and XHCI controllers wedge. According to Intel, using ADMA2 with 64-bit addressing and 96-bit descriptors serves as a workaround. Until such times when sdhci(4) has ADMA2 support, flag DMA as broken for affected interfaces. This turns out to work around the problem, too, at the cost of performance. - In the sdhci(4) ACPI front-end, probe the Intel Apollo Lake eMMC and SDXC controllers, too. 1: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/pentium-celeron-n-series-j-series-datasheet-spec-update.pdf |
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.. | ||
fsl_sdhci.c | ||
sdhci_acpi.c | ||
sdhci_fdt_gpio.c | ||
sdhci_fdt_gpio.h | ||
sdhci_fdt.c | ||
sdhci_if.m | ||
sdhci_pci.c | ||
sdhci.c | ||
sdhci.h |