347934fa63
this problem put these lines back in. While they should be unnecessary, they appear to be sometimes necessary. Reviewed in concept: dfr Approved by: re (scottl@)
303 lines
8.1 KiB
C
303 lines
8.1 KiB
C
/*-
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* Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
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*/
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#include "opt_inet.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/errno.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/ethernet.h>
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#include <net/if_llc.h>
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#include <net/if_arp.h>
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#include <net80211/ieee80211.h>
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#include <net80211/ieee80211_crypto.h>
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#include <net80211/ieee80211_node.h>
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#include <net80211/ieee80211_proto.h>
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#include <net80211/ieee80211_var.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#endif
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#include <dev/ath/if_athvar.h>
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#include <contrib/dev/ath/ah.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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/*
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* PCI glue.
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*/
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struct ath_pci_softc {
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struct ath_softc sc_sc;
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struct resource *sc_sr; /* memory resource */
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struct resource *sc_irq; /* irq resource */
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void *sc_ih; /* intererupt handler */
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u_int8_t sc_saved_intline;
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u_int8_t sc_saved_cachelinesz;
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u_int8_t sc_saved_lattimer;
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};
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#define BS_BAR 0x10
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static int
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ath_pci_probe(device_t dev)
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{
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const char* devname;
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devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
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if (devname) {
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device_set_desc(dev, devname);
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return 0;
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}
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return ENXIO;
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}
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static int
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ath_pci_attach(device_t dev)
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{
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struct ath_pci_softc *psc = device_get_softc(dev);
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struct ath_softc *sc = &psc->sc_sc;
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u_int32_t cmd;
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int error = ENXIO;
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int rid;
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bzero(psc, sizeof (*psc));
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sc->sc_dev = dev;
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cmd = pci_read_config(dev, PCIR_COMMAND, 4);
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cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, cmd, 4);
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cmd = pci_read_config(dev, PCIR_COMMAND, 4);
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if ((cmd & PCIM_CMD_MEMEN) == 0) {
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device_printf(dev, "failed to enable memory mapping\n");
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goto bad;
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}
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if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
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device_printf(dev, "failed to enable bus mastering\n");
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goto bad;
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}
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/*
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* Setup memory-mapping of PCI registers.
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*/
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rid = BS_BAR;
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psc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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0, ~0, 1, RF_ACTIVE);
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if (psc->sc_sr == NULL) {
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device_printf(dev, "cannot map register space\n");
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goto bad;
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}
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sc->sc_st = rman_get_bustag(psc->sc_sr);
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sc->sc_sh = rman_get_bushandle(psc->sc_sr);
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/*
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* Mark device invalid so any interrupts (shared or otherwise)
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* that arrive before the HAL is setup are discarded.
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*/
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sc->sc_invalid = 1;
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/*
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* Arrange interrupt line.
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*/
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rid = 0;
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psc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
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0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
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if (psc->sc_irq == NULL) {
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device_printf(dev, "could not map interrupt\n");
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goto bad1;
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}
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if (bus_setup_intr(dev, psc->sc_irq,
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INTR_TYPE_NET | INTR_MPSAFE,
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ath_intr, sc, &psc->sc_ih)) {
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device_printf(dev, "could not establish interrupt\n");
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goto bad2;
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}
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/*
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* Setup DMA descriptor area.
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*/
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if (bus_dma_tag_create(NULL, /* parent */
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1, 0, /* alignment, bounds */
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BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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0x3ffff, /* maxsize XXX */
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ATH_MAX_SCATTER, /* nsegments */
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0xffff, /* maxsegsize XXX */
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BUS_DMA_ALLOCNOW, /* flags */
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NULL, /* lockfunc */
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NULL, /* lockarg */
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&sc->sc_dmat)) {
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device_printf(dev, "cannot allocate DMA tag\n");
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goto bad3;
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}
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ATH_LOCK_INIT(sc);
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error = ath_attach(pci_get_device(dev), sc);
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if (error == 0)
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return error;
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ATH_LOCK_DESTROY(sc);
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bus_dma_tag_destroy(sc->sc_dmat);
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bad3:
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bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
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bad2:
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bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
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bad1:
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bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
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bad:
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return (error);
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}
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static int
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ath_pci_detach(device_t dev)
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{
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struct ath_pci_softc *psc = device_get_softc(dev);
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struct ath_softc *sc = &psc->sc_sc;
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/* check if device was removed */
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sc->sc_invalid = !bus_child_present(dev);
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ath_detach(sc);
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bus_generic_detach(dev);
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bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
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bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
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bus_dma_tag_destroy(sc->sc_dmat);
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bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
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ATH_LOCK_DESTROY(sc);
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return (0);
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}
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static int
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ath_pci_shutdown(device_t dev)
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{
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struct ath_pci_softc *psc = device_get_softc(dev);
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ath_shutdown(&psc->sc_sc);
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return (0);
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}
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static int
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ath_pci_suspend(device_t dev)
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{
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struct ath_pci_softc *psc = device_get_softc(dev);
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ath_suspend(&psc->sc_sc);
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psc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
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psc->sc_saved_cachelinesz= pci_read_config(dev, PCIR_CACHELNSZ, 1);
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psc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
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return (0);
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}
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static int
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ath_pci_resume(device_t dev)
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{
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struct ath_pci_softc *psc = device_get_softc(dev);
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u_int16_t cmd;
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pci_write_config(dev, PCIR_INTLINE, psc->sc_saved_intline, 1);
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pci_write_config(dev, PCIR_CACHELNSZ, psc->sc_saved_cachelinesz, 1);
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pci_write_config(dev, PCIR_LATTIMER, psc->sc_saved_lattimer, 1);
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/* re-enable mem-map and busmastering */
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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ath_resume(&psc->sc_sc);
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return (0);
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}
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static device_method_t ath_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ath_pci_probe),
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DEVMETHOD(device_attach, ath_pci_attach),
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DEVMETHOD(device_detach, ath_pci_detach),
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DEVMETHOD(device_shutdown, ath_pci_shutdown),
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DEVMETHOD(device_suspend, ath_pci_suspend),
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DEVMETHOD(device_resume, ath_pci_resume),
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{ 0,0 }
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};
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static driver_t ath_pci_driver = {
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"ath",
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ath_pci_methods,
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sizeof (struct ath_pci_softc)
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};
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static devclass_t ath_devclass;
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DRIVER_MODULE(if_ath, pci, ath_pci_driver, ath_devclass, 0, 0);
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DRIVER_MODULE(if_ath, cardbus, ath_pci_driver, ath_devclass, 0, 0);
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MODULE_VERSION(if_ath, 1);
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MODULE_DEPEND(if_ath, ath_hal, 1, 1, 1); /* Atheros HAL */
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MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
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