Only clear an EEH freeze if an error occurs. However, if an OPAL_HARDWARE error is returned, this indicates a hardware failure which cannot be unfrozen, and instead needs a hardware reset. Attempting to unfreeze a broken PCH will result in console spam for each attempt. To avoid the spam, just don't do it.
726 lines
19 KiB
C
726 lines
19 KiB
C
/*-
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* Copyright (c) 2015-2016 Nathan Whitehorn
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* Copyright (c) 2017-2018 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/pciio.h>
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#include <sys/endian.h>
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#include <sys/rman.h>
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#include <sys/vmem.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofwpci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include "pcib_if.h"
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#include "pic_if.h"
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#include "iommu_if.h"
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#include "opal.h"
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#define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL)
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#define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL)
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#define OPAL_PCI_TCE_R (1UL << 0)
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#define OPAL_PCI_TCE_W (1UL << 1)
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#define PHB3_TCE_KILL_INVAL_ALL (1UL << 63)
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/*
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* Device interface.
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*/
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static int opalpci_probe(device_t);
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static int opalpci_attach(device_t);
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/*
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* pcib interface.
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*/
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static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int,
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u_int, int);
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static void opalpci_write_config(device_t, u_int, u_int, u_int,
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u_int, u_int32_t, int);
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static int opalpci_alloc_msi(device_t dev, device_t child,
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int count, int maxcount, int *irqs);
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static int opalpci_release_msi(device_t dev, device_t child,
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int count, int *irqs);
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static int opalpci_alloc_msix(device_t dev, device_t child,
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int *irq);
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static int opalpci_release_msix(device_t dev, device_t child,
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int irq);
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static int opalpci_map_msi(device_t dev, device_t child,
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int irq, uint64_t *addr, uint32_t *data);
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static int opalpci_route_interrupt(device_t bus, device_t dev, int pin);
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/*
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* MSI PIC interface.
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*/
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static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **);
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static void opalpic_pic_eoi(device_t dev, u_int irq, void *);
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/* Bus interface */
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static bus_dma_tag_t opalpci_get_dma_tag(device_t dev, device_t child);
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/*
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* Commands
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*/
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#define OPAL_M32_WINDOW_TYPE 1
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#define OPAL_M64_WINDOW_TYPE 2
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#define OPAL_IO_WINDOW_TYPE 3
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#define OPAL_RESET_PHB_COMPLETE 1
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#define OPAL_RESET_PCI_IODA_TABLE 6
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#define OPAL_DISABLE_M64 0
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#define OPAL_ENABLE_M64_SPLIT 1
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#define OPAL_ENABLE_M64_NON_SPLIT 2
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#define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1
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#define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2
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#define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3
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#define OPAL_EEH_STOPPED_NOT_FROZEN 0
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/*
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* Constants
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*/
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#define OPAL_PCI_DEFAULT_PE 1
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#define OPAL_PCI_BUS_SPACE_LOWADDR_32BIT 0x7FFFFFFFUL
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/*
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* Driver methods.
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*/
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static device_method_t opalpci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, opalpci_probe),
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DEVMETHOD(device_attach, opalpci_attach),
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/* pcib interface */
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DEVMETHOD(pcib_read_config, opalpci_read_config),
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DEVMETHOD(pcib_write_config, opalpci_write_config),
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DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi),
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DEVMETHOD(pcib_release_msi, opalpci_release_msi),
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DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix),
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DEVMETHOD(pcib_release_msix, opalpci_release_msix),
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DEVMETHOD(pcib_map_msi, opalpci_map_msi),
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DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt),
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/* PIC interface for MSIs */
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DEVMETHOD(pic_enable, opalpic_pic_enable),
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DEVMETHOD(pic_eoi, opalpic_pic_eoi),
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/* Bus interface */
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DEVMETHOD(bus_get_dma_tag, opalpci_get_dma_tag),
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DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus),
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DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain),
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DEVMETHOD_END
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};
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struct opalpci_softc {
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struct ofw_pci_softc ofw_sc;
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uint64_t phb_id;
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vmem_t *msi_vmem;
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int msi_base; /* Base XIVE number */
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int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */
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uint64_t *tce; /* TCE table for 1:1 mapping */
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struct resource *r_reg;
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};
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static devclass_t opalpci_devclass;
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DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods,
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sizeof(struct opalpci_softc), ofw_pci_driver);
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EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, opalpci_devclass, 0, 0,
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BUS_PASS_BUS);
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static int
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opalpci_probe(device_t dev)
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{
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const char *type;
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if (opal_check() != 0)
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return (ENXIO);
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type = ofw_bus_get_type(dev);
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if (type == NULL || (strcmp(type, "pci") != 0 &&
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strcmp(type, "pciex") != 0))
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return (ENXIO);
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if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid"))
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return (ENXIO);
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device_set_desc(dev, "OPAL Host-PCI bridge");
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return (BUS_PROBE_GENERIC);
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}
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static void
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pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc)
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{
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mb();
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bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL);
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mb();
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}
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/* Simple function to round to a power of 2 */
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static uint64_t
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round_pow2(uint64_t val)
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{
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return (1 << (flsl(val + (val - 1)) - 1));
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}
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/*
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* Starting with skiboot 5.10 PCIe nodes have a new property,
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* "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us
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* to avoid hard-coding the maximum TCE size allowed, and instead provide a sane
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* default (however, the "sane" default, which works for all targets, is 64k,
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* limiting us to 64GB if we have 1M entries.
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*/
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static uint64_t
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max_tce_size(device_t dev)
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{
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phandle_t node;
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cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */
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int count;
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node = ofw_bus_get_node(dev);
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count = OF_getencprop(node, "ibm,supported-tce-sizes",
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sizes, sizeof(sizes));
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if (count < (int) sizeof(cell_t))
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return OPAL_PCI_TCE_DEFAULT_SEG_SIZE;
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count /= sizeof(cell_t);
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return (1ULL << sizes[count - 1]);
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}
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static int
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opalpci_attach(device_t dev)
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{
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struct opalpci_softc *sc;
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cell_t id[2], m64ranges[2], m64window[6], npe;
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phandle_t node;
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int i, err;
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uint64_t maxmem;
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uint64_t entries;
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uint64_t tce_size;
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uint64_t tce_tbl_size;
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int m64bar;
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int rid;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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switch (OF_getproplen(node, "ibm,opal-phbid")) {
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case 8:
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OF_getencprop(node, "ibm,opal-phbid", id, 8);
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sc->phb_id = ((uint64_t)id[0] << 32) | id[1];
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break;
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case 4:
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OF_getencprop(node, "ibm,opal-phbid", id, 4);
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sc->phb_id = id[0];
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break;
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default:
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device_printf(dev, "PHB ID property had wrong length (%zd)\n",
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OF_getproplen(node, "ibm,opal-phbid"));
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return (ENXIO);
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}
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if (bootverbose)
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device_printf(dev, "OPAL ID %#lx\n", sc->phb_id);
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rid = 0;
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sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE | RF_SHAREABLE);
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if (sc->r_reg == NULL) {
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device_printf(dev, "Failed to allocate PHB[%jd] registers\n",
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(uintmax_t)sc->phb_id);
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return (ENXIO);
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}
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#if 0
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/*
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* Reset PCI IODA table
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*/
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err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE,
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1);
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if (err != 0) {
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device_printf(dev, "IODA table reset failed: %d\n", err);
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return (ENXIO);
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}
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err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
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1);
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if (err < 0) {
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device_printf(dev, "PHB reset failed: %d\n", err);
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return (ENXIO);
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}
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if (err > 0) {
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while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
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DELAY(1000*(err + 1)); /* Returns expected delay in ms */
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}
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}
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if (err < 0) {
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device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err);
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}
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err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
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0);
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if (err < 0) {
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device_printf(dev, "PHB reset failed: %d\n", err);
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return (ENXIO);
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}
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if (err > 0) {
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while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
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DELAY(1000*(err + 1)); /* Returns expected delay in ms */
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}
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}
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#endif
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/*
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* Map all devices on the bus to partitionable endpoint one until
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* such time as we start wanting to do things like bhyve.
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*/
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err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE,
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0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER,
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OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE);
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if (err != 0) {
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device_printf(dev, "PE mapping failed: %d\n", err);
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return (ENXIO);
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}
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/*
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* Turn on MMIO, mapped to PE 1
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*/
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if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4)
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npe = 1;
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for (i = 0; i < npe; i++) {
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err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
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OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i);
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if (err != 0)
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device_printf(dev, "MMIO %d map failed: %d\n", i, err);
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}
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if (OF_getencprop(node, "ibm,opal-available-m64-ranges",
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m64ranges, sizeof(m64ranges)) == sizeof(m64ranges))
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m64bar = m64ranges[0];
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else
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m64bar = 0;
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/* XXX: multiple M64 windows? */
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if (OF_getencprop(node, "ibm,opal-m64-window",
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m64window, sizeof(m64window)) == sizeof(m64window)) {
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opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
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OPAL_M64_WINDOW_TYPE, m64bar, 0);
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opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id,
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OPAL_M64_WINDOW_TYPE, m64bar /* index */,
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((uint64_t)m64window[2] << 32) | m64window[3], 0,
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((uint64_t)m64window[4] << 32) | m64window[5]);
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opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
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OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE,
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m64bar /* index */, 0);
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opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
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OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT);
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}
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/*
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* Enable IOMMU for PE1 - map everything 1:1 using
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* segments of max_tce_size size
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*/
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tce_size = max_tce_size(dev);
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maxmem = roundup2(powerpc_ptob(Maxmem), tce_size);
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entries = round_pow2(maxmem / tce_size);
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tce_tbl_size = MAX(entries * sizeof(uint64_t), 4096);
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if (entries > OPAL_PCI_TCE_MAX_ENTRIES)
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panic("POWERNV supports only %jdGB of memory space\n",
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(uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30));
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if (bootverbose)
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device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem);
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sc->tce = contigmalloc(tce_tbl_size,
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M_DEVBUF, M_NOWAIT | M_ZERO, 0,
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BUS_SPACE_MAXADDR, tce_tbl_size, 0);
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if (sc->tce == NULL)
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panic("Failed to allocate TCE memory for PHB %jd\n",
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(uintmax_t)sc->phb_id);
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for (i = 0; i < entries; i++)
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sc->tce[i] = (i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W;
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/* Map TCE for every PE. It seems necessary for Power8 */
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for (i = 0; i < npe; i++) {
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err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id,
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i, (i << 1),
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1, pmap_kextract((uint64_t)&sc->tce[0]),
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tce_tbl_size, tce_size);
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if (err != 0) {
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device_printf(dev, "DMA IOMMU mapping failed: %d\n", err);
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return (ENXIO);
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}
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err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id,
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i, (i << 1) + 1,
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(1UL << 59), maxmem);
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if (err != 0) {
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device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err);
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return (ENXIO);
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}
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}
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/*
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* Invalidate all previous TCE entries.
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*
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* TODO: add support for other PHBs than PHB3
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*/
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pci_phb3_tce_invalidate_entire(sc);
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/*
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* Get MSI properties
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*/
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sc->msi_vmem = NULL;
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if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) {
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cell_t msi_ranges[2];
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OF_getencprop(node, "ibm,opal-msi-ranges",
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msi_ranges, sizeof(msi_ranges));
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sc->msi_base = msi_ranges[0];
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sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0],
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msi_ranges[1], 1, 16, M_BESTFIT | M_WAITOK);
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sc->base_msi_irq = powerpc_register_pic(dev,
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OF_xref_from_node(node),
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msi_ranges[0] + msi_ranges[1], 0, FALSE);
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if (bootverbose)
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device_printf(dev, "Supports %d MSIs starting at %d\n",
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msi_ranges[1], msi_ranges[0]);
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}
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/* Create the parent DMA tag */
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/*
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* Constrain it to POWER8 PHB (ioda2) for now. It seems to mess up on
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* POWER9 systems.
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*/
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if (ofw_bus_is_compatible(dev, "ibm,ioda2-phb")) {
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err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
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1, 0, /* alignment, bounds */
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|
OPAL_PCI_BUS_SPACE_LOWADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR_32BIT, /* highaddr */
|
|
NULL, NULL, /* filter, filterarg */
|
|
BUS_SPACE_MAXSIZE, /* maxsize */
|
|
BUS_SPACE_UNRESTRICTED, /* nsegments */
|
|
BUS_SPACE_MAXSIZE, /* maxsegsize */
|
|
0, /* flags */
|
|
NULL, NULL, /* lockfunc, lockarg */
|
|
&sc->ofw_sc.sc_dmat);
|
|
if (err != 0) {
|
|
device_printf(dev, "Failed to create DMA tag\n");
|
|
return (err);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* General OFW PCI attach
|
|
*/
|
|
err = ofw_pci_init(dev);
|
|
if (err != 0)
|
|
return (err);
|
|
|
|
/*
|
|
* Unfreeze non-config-space PCI operations. Let this fail silently
|
|
* if e.g. there is no current freeze.
|
|
*/
|
|
opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE,
|
|
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
|
|
|
|
/*
|
|
* OPAL stores 64-bit BARs in a special property rather than "ranges"
|
|
*/
|
|
if (OF_getencprop(node, "ibm,opal-m64-window",
|
|
m64window, sizeof(m64window)) == sizeof(m64window)) {
|
|
struct ofw_pci_range *rp;
|
|
|
|
sc->ofw_sc.sc_nrange++;
|
|
sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range,
|
|
sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]),
|
|
M_DEVBUF, M_WAITOK);
|
|
rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1];
|
|
rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 |
|
|
OFW_PCI_PHYS_HI_PREFETCHABLE;
|
|
rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1];
|
|
rp->host = ((uint64_t)m64window[2] << 32) | m64window[3];
|
|
rp->size = ((uint64_t)m64window[4] << 32) | m64window[5];
|
|
rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci,
|
|
rp->pci + rp->size - 1);
|
|
}
|
|
|
|
return (ofw_pci_attach(dev));
|
|
}
|
|
|
|
static uint32_t
|
|
opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
|
|
int width)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
uint64_t config_addr;
|
|
uint8_t byte, eeh_state;
|
|
uint16_t half;
|
|
uint32_t word;
|
|
int error;
|
|
uint16_t err_type;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
|
|
|
|
switch (width) {
|
|
case 1:
|
|
error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id,
|
|
config_addr, reg, vtophys(&byte));
|
|
word = byte;
|
|
break;
|
|
case 2:
|
|
error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id,
|
|
config_addr, reg, vtophys(&half));
|
|
word = half;
|
|
break;
|
|
case 4:
|
|
error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id,
|
|
config_addr, reg, vtophys(&word));
|
|
break;
|
|
default:
|
|
error = OPAL_SUCCESS;
|
|
word = 0xffffffff;
|
|
}
|
|
|
|
/*
|
|
* Poking config state for non-existant devices can make
|
|
* the host bridge hang up. Clear any errors.
|
|
*
|
|
* XXX: Make this conditional on the existence of a freeze
|
|
*/
|
|
|
|
if (error != OPAL_SUCCESS) {
|
|
if (error != OPAL_HARDWARE) {
|
|
opal_call(OPAL_PCI_EEH_FREEZE_STATUS, sc->phb_id,
|
|
OPAL_PCI_DEFAULT_PE, vtophys(&eeh_state),
|
|
vtophys(&err_type), NULL);
|
|
if (eeh_state != OPAL_EEH_STOPPED_NOT_FROZEN)
|
|
opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
|
|
sc->phb_id, OPAL_PCI_DEFAULT_PE,
|
|
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
|
|
}
|
|
word = 0xffffffff;
|
|
}
|
|
|
|
return (word);
|
|
}
|
|
|
|
static void
|
|
opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
|
u_int reg, uint32_t val, int width)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
uint64_t config_addr;
|
|
int error = OPAL_SUCCESS;
|
|
uint16_t err_type;
|
|
uint8_t eeh_state;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
|
|
|
|
switch (width) {
|
|
case 1:
|
|
error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id,
|
|
config_addr, reg, val);
|
|
break;
|
|
case 2:
|
|
error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id,
|
|
config_addr, reg, val);
|
|
break;
|
|
case 4:
|
|
error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id,
|
|
config_addr, reg, val);
|
|
break;
|
|
}
|
|
|
|
if (error != OPAL_SUCCESS) {
|
|
/*
|
|
* Poking config state for non-existant devices can make
|
|
* the host bridge hang up. Clear any errors.
|
|
*/
|
|
if (error != OPAL_HARDWARE) {
|
|
opal_call(OPAL_PCI_EEH_FREEZE_STATUS, sc->phb_id,
|
|
OPAL_PCI_DEFAULT_PE, vtophys(&eeh_state),
|
|
vtophys(&err_type), NULL);
|
|
if (eeh_state != OPAL_EEH_STOPPED_NOT_FROZEN)
|
|
opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
|
|
sc->phb_id, OPAL_PCI_DEFAULT_PE,
|
|
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
opalpci_route_interrupt(device_t bus, device_t dev, int pin)
|
|
{
|
|
|
|
return (pin);
|
|
}
|
|
|
|
static int
|
|
opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount,
|
|
int *irqs)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
vmem_addr_t start;
|
|
phandle_t xref;
|
|
int err, i;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (sc->msi_vmem == NULL)
|
|
return (ENODEV);
|
|
|
|
err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0,
|
|
VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
|
|
|
|
if (err)
|
|
return (err);
|
|
|
|
xref = OF_xref_from_node(ofw_bus_get_node(dev));
|
|
for (i = 0; i < count; i++)
|
|
irqs[i] = MAP_IRQ(xref, start + i);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
opalpci_release_msi(device_t dev, device_t child, int count, int *irqs)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (sc->msi_vmem == NULL)
|
|
return (ENODEV);
|
|
|
|
vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
opalpci_alloc_msix(device_t dev, device_t child, int *irq)
|
|
{
|
|
return (opalpci_alloc_msi(dev, child, 1, 1, irq));
|
|
}
|
|
|
|
static int
|
|
opalpci_release_msix(device_t dev, device_t child, int irq)
|
|
{
|
|
return (opalpci_release_msi(dev, child, 1, &irq));
|
|
}
|
|
|
|
static int
|
|
opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
|
|
uint32_t *data)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
struct pci_devinfo *dinfo;
|
|
int err, xive;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (sc->msi_vmem == NULL)
|
|
return (ENODEV);
|
|
|
|
xive = irq - sc->base_msi_irq - sc->msi_base;
|
|
opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive);
|
|
|
|
dinfo = device_get_ivars(child);
|
|
if (dinfo->cfg.msi.msi_alloc > 0 &&
|
|
(dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) {
|
|
uint32_t msi32;
|
|
err = opal_call(OPAL_GET_MSI_32, sc->phb_id,
|
|
OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32),
|
|
vtophys(data));
|
|
*addr = be32toh(msi32);
|
|
} else {
|
|
err = opal_call(OPAL_GET_MSI_64, sc->phb_id,
|
|
OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data));
|
|
*addr = be64toh(*addr);
|
|
}
|
|
*data = be32toh(*data);
|
|
|
|
if (bootverbose && err != 0)
|
|
device_printf(child, "OPAL MSI mapping error: %d\n", err);
|
|
|
|
return ((err == 0) ? 0 : ENXIO);
|
|
}
|
|
|
|
static void
|
|
opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **priv)
|
|
{
|
|
struct opalpci_softc *sc = device_get_softc(dev);
|
|
|
|
PIC_ENABLE(root_pic, irq, vector, priv);
|
|
opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq, priv);
|
|
}
|
|
|
|
static void opalpic_pic_eoi(device_t dev, u_int irq, void *priv)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq);
|
|
|
|
PIC_EOI(root_pic, irq, priv);
|
|
}
|
|
|
|
static bus_dma_tag_t
|
|
opalpci_get_dma_tag(device_t dev, device_t child)
|
|
{
|
|
struct opalpci_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
return (sc->ofw_sc.sc_dmat);
|
|
}
|