Peter Wemm 40a7c81112 CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32. This should ... probably be 128 since that is what the hardware prefetch fill size is on both the p3, p4 and athlon* cpus.		2003-12-11 04:47:53 +00:00
..
elf_rtld.x
lockdflt.c	CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32. This should	2003-12-11 04:47:53 +00:00
Makefile.inc
reloc.c	Initial pass at supporting shared libraries on amd64. There are still	2003-05-24 17:37:51 +00:00
rtld_machdep.h	Allow threading libraries to register their own locking	2003-05-29 22:58:26 +00:00
rtld_start.S	Initial pass at supporting shared libraries on amd64. There are still	2003-05-24 17:37:51 +00:00