2dd1bdf183
Summary: Migrate to using the semi-opaque type rman_res_t to specify rman resources. For now, this is still compatible with u_long. This is step one in migrating rman to use uintmax_t for resources instead of u_long. Going forward, this could feasibly be used to specify architecture-specific definitions of resource ranges, rather than baking a specific integer type into the API. This change has been broken out to facilitate MFC'ing drivers back to 10 without breaking ABI. Reviewed By: jhb Sponsored by: Alex Perez/Inertial Computing Differential Revision: https://reviews.freebsd.org/D5075
467 lines
9.7 KiB
C
467 lines
9.7 KiB
C
/*-
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* Copyright (c) 2006 Olivier Houchard
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/xscale/i8134x/i81342reg.h>
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#include <arm/xscale/i8134x/i81342var.h>
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#define WDTCR_ENABLE1 0x1e1e1e1e
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#define WDTCR_ENABLE2 0xe1e1e1e1
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static volatile int intr_enabled0;
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static volatile int intr_enabled1;
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static volatile int intr_enabled2;
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static volatile int intr_enabled3;
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struct bus_space i81342_bs_tag;
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/* Read the interrupt pending register */
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static __inline
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uint32_t intpnd0_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c0, c3, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intpnd1_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c1, c3, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intpnd2_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c2, c3, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intpnd3_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c3, c3, 0"
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: "=r" (ret));
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return (ret);
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}
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/* Read the interrupt control register */
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/* 0 masked, 1 unmasked */
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static __inline
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uint32_t intctl0_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c0, c4, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intctl1_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c1, c4, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intctl2_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c2, c4, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intctl3_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c3, c4, 0"
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: "=r" (ret));
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return (ret);
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}
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/* Write the interrupt control register */
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static __inline
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void intctl0_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c0, c4, 0"
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: : "r" (val));
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}
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static __inline
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void intctl1_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c1, c4, 0"
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: : "r" (val));
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}
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static __inline
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void intctl2_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c2, c4, 0"
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: : "r" (val));
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}
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static __inline
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void intctl3_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c3, c4, 0"
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: : "r" (val));
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}
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/* Read the interrupt steering register */
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/* 0 IRQ 1 FIQ */
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static __inline
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uint32_t intstr0_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c0, c5, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intstr1_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c1, c5, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intstr2_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c2, c5, 0"
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: "=r" (ret));
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return (ret);
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}
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static __inline
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uint32_t intstr3_read(void)
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{
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uint32_t ret;
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__asm __volatile("mrc p6, 0, %0, c3, c5, 0"
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: "=r" (ret));
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return (ret);
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}
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/* Write the interrupt steering register */
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static __inline
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void intstr0_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c0, c5, 0"
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: : "r" (val));
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}
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static __inline
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void intstr1_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c1, c5, 0"
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: : "r" (val));
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}
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static __inline
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void intstr2_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c2, c5, 0"
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: : "r" (val));
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}
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static __inline
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void intstr3_write(uint32_t val)
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{
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__asm __volatile("mcr p6, 0, %0, c3, c5, 0"
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: : "r" (val));
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}
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void
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cpu_reset(void)
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{
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disable_interrupts(PSR_I);
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/* XXX: Use the watchdog to reset for now */
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__asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
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"mcr p6, 0, %1, c7, c9, 0\n"
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"mcr p6, 0, %2, c7, c9, 0\n"
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: : "r" (1), "r" (WDTCR_ENABLE1), "r" (WDTCR_ENABLE2));
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while (1);
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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if (nb < 32) {
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intr_enabled0 &= ~(1 << nb);
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intctl0_write(intr_enabled0);
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} else if (nb < 64) {
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intr_enabled1 &= ~(1 << (nb - 32));
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intctl1_write(intr_enabled1);
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} else if (nb < 96) {
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intr_enabled2 &= ~(1 << (nb - 64));
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intctl2_write(intr_enabled2);
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} else {
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intr_enabled3 &= ~(1 << (nb - 96));
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intctl3_write(intr_enabled3);
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}
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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if (nb < 32) {
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intr_enabled0 |= (1 << nb);
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intctl0_write(intr_enabled0);
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} else if (nb < 64) {
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intr_enabled1 |= (1 << (nb - 32));
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intctl1_write(intr_enabled1);
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} else if (nb < 96) {
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intr_enabled2 |= (1 << (nb - 64));
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intctl2_write(intr_enabled2);
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} else {
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intr_enabled3 |= (1 << (nb - 96));
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intctl3_write(intr_enabled3);
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}
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}
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int
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arm_get_next_irq(int last __unused)
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{
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uint32_t val;
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val = intpnd0_read() & intr_enabled0;
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if (val)
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return (ffs(val) - 1);
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val = intpnd1_read() & intr_enabled1;
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if (val)
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return (32 + ffs(val) - 1);
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val = intpnd2_read() & intr_enabled2;
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if (val)
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return (64 + ffs(val) - 1);
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val = intpnd3_read() & intr_enabled3;
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if (val)
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return (96 + ffs(val) - 1);
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return (-1);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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static int
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i81342_probe(device_t dev)
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{
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unsigned int freq;
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freq = *(volatile unsigned int *)(IOP34X_VADDR + IOP34X_PFR);
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switch (freq & IOP34X_FREQ_MASK) {
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case IOP34X_FREQ_600:
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device_set_desc(dev, "Intel 81342 600MHz");
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break;
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case IOP34X_FREQ_667:
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device_set_desc(dev, "Intel 81342 667MHz");
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break;
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case IOP34X_FREQ_800:
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device_set_desc(dev, "Intel 81342 800MHz");
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break;
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case IOP34X_FREQ_833:
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device_set_desc(dev, "Intel 81342 833MHz");
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break;
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case IOP34X_FREQ_1000:
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device_set_desc(dev, "Intel 81342 1000MHz");
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break;
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case IOP34X_FREQ_1200:
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device_set_desc(dev, "Intel 81342 1200MHz");
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break;
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default:
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device_set_desc(dev, "Intel 81342 unknown frequency");
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break;
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}
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return (0);
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}
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static void
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i81342_identify(driver_t *driver, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "iq", 0);
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}
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static int
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i81342_attach(device_t dev)
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{
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struct i81342_softc *sc = device_get_softc(dev);
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uint32_t esstrsr;
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i81342_bs_init(&i81342_bs_tag, sc);
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sc->sc_st = &i81342_bs_tag;
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sc->sc_sh = IOP34X_VADDR;
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esstrsr = bus_space_read_4(sc->sc_st, sc->sc_sh, IOP34X_ESSTSR0);
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sc->sc_atux_sh = IOP34X_ATUX_ADDR(esstrsr) - IOP34X_HWADDR +
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IOP34X_VADDR;
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sc->sc_atue_sh = IOP34X_ATUE_ADDR(esstrsr) - IOP34X_HWADDR +
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IOP34X_VADDR;
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/* Disable all interrupts. */
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intctl0_write(0);
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intctl1_write(0);
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intctl2_write(0);
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intctl3_write(0);
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/* Defaults to IRQ */
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intstr0_write(0);
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intstr1_write(0);
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intstr2_write(0);
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intstr3_write(0);
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "i81342 IRQs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, 0, 127) != 0)
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panic("i81342_attach: failed to set up IRQ rman");
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device_add_child(dev, "obio", 0);
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device_add_child(dev, "itimer", 0);
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device_add_child(dev, "iopwdog", 0);
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device_add_child(dev, "pcib", 0);
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device_add_child(dev, "pcib", 1);
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device_add_child(dev, "iqseg", 0);
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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return (0);
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}
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static struct resource *
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i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct i81342_softc *sc = device_get_softc(dev);
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struct resource *rv;
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if (type == SYS_RES_IRQ) {
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rv = rman_reserve_resource(&sc->sc_irq_rman,
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start, end, count, flags, child);
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if (rv != NULL)
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rman_set_rid(rv, *rid);
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return (rv);
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}
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return (NULL);
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}
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static int
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i81342_setup_intr(device_t dev, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
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void **cookiep)
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{
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int error;
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error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
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filt, intr, arg, cookiep);
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if (error)
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return (error);
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return (0);
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}
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static int
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i81342_teardown_intr(device_t dev, device_t child, struct resource *res,
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void *cookie)
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{
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return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
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}
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static device_method_t i81342_methods[] = {
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DEVMETHOD(device_probe, i81342_probe),
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DEVMETHOD(device_attach, i81342_attach),
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DEVMETHOD(device_identify, i81342_identify),
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DEVMETHOD(bus_alloc_resource, i81342_alloc_resource),
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DEVMETHOD(bus_setup_intr, i81342_setup_intr),
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DEVMETHOD(bus_teardown_intr, i81342_teardown_intr),
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{0, 0},
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};
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static driver_t i81342_driver = {
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"iq",
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i81342_methods,
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sizeof(struct i81342_softc),
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};
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static devclass_t i81342_devclass;
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DRIVER_MODULE(iq, nexus, i81342_driver, i81342_devclass, 0, 0);
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