40a7c81112
probably be 128 since that is what the hardware prefetch fill size is on both the p3, p4 and athlon* cpus.
203 lines
5.5 KiB
C
203 lines
5.5 KiB
C
/*-
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* Copyright 1999, 2000 John D. Polstra.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Thread locking implementation for the dynamic linker.
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*
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* On 80486 and later CPUs we use the "simple, non-scalable
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* reader-preference lock" from:
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*
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* J. M. Mellor-Crummey and M. L. Scott. "Scalable Reader-Writer
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* Synchronization for Shared-Memory Multiprocessors." 3rd ACM Symp. on
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* Principles and Practice of Parallel Programming, April 1991.
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*
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* In this algorithm the lock is a single word. Its low-order bit is
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* set when a writer holds the lock. The remaining high-order bits
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* contain a count of readers desiring the lock. The algorithm requires
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* atomic "compare_and_store" and "add" operations.
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*
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* The "compare_and_store" operation requires the "cmpxchg" instruction
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* on the x86. Unfortunately, the 80386 CPU does not support that
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* instruction -- only the 80486 and later models support it. So on the
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* 80386 we must use simple test-and-set exclusive locks instead. We
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* determine which kind of lock to use by trying to execute a "cmpxchg"
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* instruction and catching the SIGILL which results on the 80386.
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*/
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#include <signal.h>
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#include <stdlib.h>
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#include <time.h>
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#include "debug.h"
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#include "rtld.h"
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#define CACHE_LINE_SIZE 64
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#define WAFLAG 0x1 /* A writer holds the lock */
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#define RC_INCR 0x2 /* Adjusts count of readers desiring lock */
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typedef struct Struct_Lock {
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volatile int lock;
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void *base;
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} Lock;
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static sigset_t fullsigmask, oldsigmask;
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static inline int
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cmpxchgl(int old, int new, volatile int *m)
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{
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int result;
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__asm __volatile ("lock; cmpxchgl %2, %0"
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: "+m"(*m), "=a"(result)
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: "r"(new), "1"(old)
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: "cc");
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return result;
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}
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static inline int
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xchgl(int v, volatile int *m)
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{
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int result;
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__asm __volatile ("xchgl %0, %1"
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: "=r"(result), "+m"(*m)
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: "0"(v));
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return result;
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}
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static void *
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lock_create(void *context)
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{
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void *base;
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char *p;
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uintptr_t r;
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Lock *l;
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/*
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* Arrange for the lock to occupy its own cache line. First, we
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* optimistically allocate just a cache line, hoping that malloc
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* will give us a well-aligned block of memory. If that doesn't
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* work, we allocate a larger block and take a well-aligned cache
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* line from it.
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*/
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base = xmalloc(CACHE_LINE_SIZE);
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p = (char *)base;
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if ((uintptr_t)p % CACHE_LINE_SIZE != 0) {
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free(base);
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base = xmalloc(2 * CACHE_LINE_SIZE);
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p = (char *)base;
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if ((r = (uintptr_t)p % CACHE_LINE_SIZE) != 0)
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p += CACHE_LINE_SIZE - r;
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}
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l = (Lock *)p;
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l->base = base;
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l->lock = 0;
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return l;
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}
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static void
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lock_destroy(void *lock)
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{
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Lock *l = (Lock *)lock;
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free(l->base);
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}
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/*
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* Better reader/writer locks for the 80486 and later CPUs.
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*/
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static void
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rlock_acquire(void *lock)
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{
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Lock *l = (Lock *)lock;
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atomic_add_int(&l->lock, RC_INCR);
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while (l->lock & WAFLAG)
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; /* Spin */
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}
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static void
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wlock_acquire(void *lock)
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{
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Lock *l = (Lock *)lock;
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sigset_t tmp_oldsigmask;
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for ( ; ; ) {
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sigprocmask(SIG_BLOCK, &fullsigmask, &tmp_oldsigmask);
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if (cmpxchgl(0, WAFLAG, &l->lock) == 0)
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break;
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sigprocmask(SIG_SETMASK, &tmp_oldsigmask, NULL);
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}
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oldsigmask = tmp_oldsigmask;
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}
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static void
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rlock_release(void *lock)
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{
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Lock *l = (Lock *)lock;
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atomic_add_int(&l->lock, -RC_INCR);
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}
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static void
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wlock_release(void *lock)
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{
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Lock *l = (Lock *)lock;
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atomic_add_int(&l->lock, -WAFLAG);
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sigprocmask(SIG_SETMASK, &oldsigmask, NULL);
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}
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void
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lockdflt_init(LockInfo *li)
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{
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li->context = NULL;
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li->context_destroy = NULL;
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li->lock_create = lock_create;
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li->lock_destroy = lock_destroy;
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li->rlock_acquire = rlock_acquire;
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li->wlock_acquire = wlock_acquire;
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li->rlock_release = rlock_release;
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li->wlock_release = wlock_release;
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/*
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* Construct a mask to block all signals except traps which might
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* conceivably be generated within the dynamic linker itself.
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*/
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sigfillset(&fullsigmask);
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sigdelset(&fullsigmask, SIGILL);
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sigdelset(&fullsigmask, SIGTRAP);
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sigdelset(&fullsigmask, SIGABRT);
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sigdelset(&fullsigmask, SIGEMT);
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sigdelset(&fullsigmask, SIGFPE);
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sigdelset(&fullsigmask, SIGBUS);
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sigdelset(&fullsigmask, SIGSEGV);
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sigdelset(&fullsigmask, SIGSYS);
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}
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